From 8e4e0a6993639d06d777227d499d15df935aa6a2 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 8 Mar 2021 15:16:42 -0500 Subject: [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR The TW and TSR fields should be bits 21 and 22 and not 30/29. This was found while comparing QEMU behaviour against the sail formal model (https://github.com/rems-project/sail-riscv/). Backports 529577457cbba9e429af629c46204f63e50fa832 --- qemu/target/riscv/cpu_bits.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/riscv/cpu_bits.h b/qemu/target/riscv/cpu_bits.h index 53a25b04..487d65b2 100644 --- a/qemu/target/riscv/cpu_bits.h +++ b/qemu/target/riscv/cpu_bits.h @@ -379,8 +379,8 @@ #define MSTATUS_MXR 0x00080000 #define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ -#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ -#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ +#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ +#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL