From 8daabd339e6271284d80e72b15044807a085a0f9 Mon Sep 17 00:00:00 2001 From: Miodrag Dinic Date: Sat, 3 Mar 2018 22:08:04 -0500 Subject: [PATCH] target/mips: fix msa copy_[s|u]_df rd = 0 corner case This patch fixes the msa copy_[s|u]_df instruction emulation when the destination register rd is zero. Without this patch the zero register would get clobbered, which should never happen because it is supposed to be hardwired to 0. Fix this corner case by explicitly checking rd = 0 and effectively making these instructions emulation no-op in that case. Backports commit cab4888136a92250fdd401402622824994f7ce0b from qemu --- qemu/target/mips/translate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index e56940a8..889de1dc 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -18819,10 +18819,14 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: - gen_helper_msa_copy_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn); + if (likely(wd != 0)) { + gen_helper_msa_copy_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn); + } break; case OPC_COPY_U_df: - gen_helper_msa_copy_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn); + if (likely(wd != 0)) { + gen_helper_msa_copy_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn); + } break; case OPC_INSERT_df: gen_helper_msa_insert_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);