From 858aa2d094d8ef763c2869351478ffa8af0fdac1 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 22 Aug 2018 12:48:32 -0400 Subject: [PATCH] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2 The AArch32 HSR is the equivalent of AArch64 ESR_EL2; we can implement it by marking our existing ESR_EL2 regdef as STATE_BOTH. It also needs to be "RES0 from EL3 if EL2 not implemented", so add the missing stanza to el3_no_el2_cp_reginfo. Backports commit 68e78e332cb1c3f8b0317a0443acb2b5e190f0dd from qemu --- qemu/target/arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index b2e78d53..a840e4ab 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -3352,6 +3352,8 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { { "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_NO_RAW, PL2_RW, 0, NULL, 0, 0, {0, 0}, NULL, arm_cp_read_zero, arm_cp_write_ignore }, + { "ESR_EL2", 0,5,2, 3,1,0, ARM_CP_STATE_BOTH, ARM_CP_CONST, + PL2_RW, 0, NULL, 0 }, { "CPTR_EL2", 0,1,1, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST, PL2_RW, 0, NULL, 0 }, { "MAIR_EL2", 0,10,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST, @@ -3451,7 +3453,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { NULL, NULL, hcr_write }, { "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) }, - { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64, 0, + { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_BOTH, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) }, { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },