From 7b0c98c236fbb2350e6cd8ded43784ff7bdc6cd9 Mon Sep 17 00:00:00 2001
From: Claudio Fontana <cfontana@suse.de>
Date: Thu, 4 Mar 2021 17:24:30 -0500
Subject: [PATCH] cpu: move adjust_watchpoint_address to tcg_ops

commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")

introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.

Make adjust_watchpoint_address optional and move it to tcg_ops.

Backports 9ea9087bb4a86893e4ac6ff643837937dc9e5849
---
 qemu/exec.c            | 2 +-
 qemu/include/qom/cpu.h | 6 ++++--
 qemu/qom/cpu.c         | 2 +-
 qemu/target/arm/cpu.c  | 2 +-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/qemu/exec.c b/qemu/exec.c
index b2bf3d8d..29278d18 100644
--- a/qemu/exec.c
+++ b/qemu/exec.c
@@ -869,7 +869,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
         return;
     }
 
-    addr = cc->adjust_watchpoint_address(cpu, addr, len);
+    addr = cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len);
     QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
         if (watchpoint_address_matches(wp, addr, len)
             && (wp->flags & flags)) {
diff --git a/qemu/include/qom/cpu.h b/qemu/include/qom/cpu.h
index ffb23b78..f6debd69 100644
--- a/qemu/include/qom/cpu.h
+++ b/qemu/include/qom/cpu.h
@@ -135,6 +135,10 @@ typedef struct TcgCpuOperations {
     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
                                 MMUAccessType access_type,
                                 int mmu_idx, uintptr_t retaddr);
+    /**
+     * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
+     */
+    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
 
 } TcgCpuOperations;
 
@@ -208,8 +212,6 @@ typedef struct CPUClass {
 
     const struct VMStateDescription *vmsd;
 
-    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
-
     /* Keep non-pointer data at the end to minimize holes.  */
     TcgCpuOperations tcg_ops;
     bool tcg_initialized;
diff --git a/qemu/qom/cpu.c b/qemu/qom/cpu.c
index c989fb2f..f8558f77 100644
--- a/qemu/qom/cpu.c
+++ b/qemu/qom/cpu.c
@@ -295,10 +295,10 @@ static void cpu_class_init(struct uc_struct *uc, ObjectClass *klass, void *data)
     k->get_memory_mapping = cpu_common_get_memory_mapping;
     k->tcg_ops.debug_excp_handler = cpu_common_noop;
     k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
+    k->tcg_ops.adjust_watchpoint_address = cpu_adjust_watchpoint_address;
     k->tcg_ops.cpu_exec_enter = cpu_common_noop;
     k->tcg_ops.cpu_exec_exit = cpu_common_noop;
     k->tcg_ops.cpu_exec_interrupt = cpu_common_exec_interrupt;
-    k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
     dc->realize = cpu_common_realizefn;
     /*
      * Reason: CPUs still need special care by board code: wiring up
diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c
index 68a1d86e..dc932c41 100644
--- a/qemu/target/arm/cpu.c
+++ b/qemu/target/arm/cpu.c
@@ -2116,7 +2116,7 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
 #if !defined(CONFIG_USER_ONLY)
     cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
     cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
-    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+    cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
     cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
 #endif
 #endif /* CONFIG_TCG */