diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c
index cae1e7b3..00b852c2 100644
--- a/qemu/target/arm/translate-sve.c
+++ b/qemu/target/arm/translate-sve.c
@@ -4832,8 +4832,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
         TCGv_i64 addr = new_tmp_a64(s);
-        tcg_gen_muli_i64(tcg_ctx, addr, cpu_reg(s, a->rm),
-                         (a->nreg + 1) << dtype_msz(a->dtype));
+        tcg_gen_shli_i64(tcg_ctx, addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
         tcg_gen_add_i64(tcg_ctx, addr, addr, cpu_reg_sp(s, a->rn));
         do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg);
     }
@@ -5074,7 +5073,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn)
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
         TCGv_i64 addr = new_tmp_a64(s);
-        tcg_gen_muli_i64(tcg_ctx, addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz);
+        tcg_gen_shli_i64(tcg_ctx, addr, cpu_reg(s, a->rm), a->msz);
         tcg_gen_add_i64(tcg_ctx, addr, addr, cpu_reg_sp(s, a->rn));
         do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg);
     }