diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 92321701..ccc7685c 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -311,8 +311,6 @@ typedef struct CPUARMState {
             uint64_t par_el[4];
         };
 
-        uint32_t c6_rgnr;
-
         uint32_t c9_insn; /* Cache lockdown registers.  */
         uint32_t c9_data;
         uint64_t c9_pmcr; /* performance monitor control register */
@@ -526,6 +524,7 @@ typedef struct CPUARMState {
         uint32_t *drbar;
         uint32_t *drsr;
         uint32_t *dracr;
+        uint32_t rnr;
     } pmsav7;
 
     void *nvic;
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index 87b7c36d..619fa171 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -2147,7 +2147,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
         return 0;
     }
 
-    u32p += env->cp15.c6_rgnr;
+    u32p += env->pmsav7.rnr;
     return *u32p;
 }
 
@@ -2161,7 +2161,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
         return;
     }
 
-    u32p += env->cp15.c6_rgnr;
+    u32p += env->pmsav7.rnr;
     tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
     *u32p = value;
 }
@@ -2205,7 +2205,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
       PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0},
       NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
     { "RGNR", 15,6,2, 0,0,0, 0,0,
-      PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_rgnr), {0, 0},
+      PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr), {0, 0},
       NULL, NULL, pmsav7_rgnr_write },
     REGINFO_SENTINEL
 };