From 6a015761ac2c886a0cdfb31e6b155355c2bb6a4d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 30 Apr 2020 07:21:15 -0400 Subject: [PATCH] target/arm: Remove obsolete TODO note from get_phys_addr_lpae() An old comment in get_phys_addr_lpae() claims that the code does not support the different format TCR for VTCR_EL2. This used to be true but it is not true now (in particular the aa64_va_parameters() and aa32_va_parameters() functions correctly handle the different register format by checking whether the mmu_idx is Stage2). Remove the out of date parts of the comment. Backports commit 07d1be3b3aac20c21ac4a95c7f3f01a3622a31a3 from qemu --- qemu/target/arm/helper.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 64a67087..8dfa962c 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -10513,13 +10513,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; - /* - * TODO: - * This code does not handle the different format TCR for VTCR_EL2. - * This code also does not support shareability levels. - * Attribute and permission bit handling should also be checked when adding - * support for those page table walks. - */ + /* TODO: This code does not support shareability levels. */ if (aarch64) { param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH);