From 6681fea03229bcb81e132dba3ec555ea9fc0b095 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 15 Feb 2018 09:04:06 -0500 Subject: [PATCH] target-arm: Implement missing ACTLR registers We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and ACTLR_EL3, for consistency. Since we don't currently have any CPUs that need the EL2/EL3 versions to reset to non-zero values, implement as RAZ/WI. Backports commit 834a6c6920316d39aaf0e68ac936c0a3ad164815 from qemu --- qemu/target-arm/helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 31dcba33..4305de58 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -3366,11 +3366,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_AUXCR)) { - ARMCPRegInfo auxcr = { - "ACTLR_EL1", 0,1,0, 3,0,1, ARM_CP_STATE_BOTH, - ARM_CP_CONST, PL1_RW, 0, NULL, cpu->reset_auxcr + ARMCPRegInfo auxcr_reginfo[] = { + { "ACTLR_EL1", 0,1,0, 3,0,1, ARM_CP_STATE_BOTH, + ARM_CP_CONST, PL1_RW, 0, NULL, cpu->reset_auxcr }, + { "ACTLR_EL2",0,1,0, 3,4,1, ARM_CP_STATE_BOTH, ARM_CP_CONST, + PL2_RW, 0, NULL, 0 }, + { "ACTLR_EL3", 0,1,0, 3,6,1, ARM_CP_STATE_AA64, ARM_CP_CONST, + PL3_RW, 0, NULL, 0 }, + REGINFO_SENTINEL }; - define_one_arm_cp_reg(cpu, &auxcr); + define_arm_cp_regs(cpu, auxcr_reginfo); } if (arm_feature(env, ARM_FEATURE_CBAR)) {