diff --git a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
index 7e0e2d39..86105c9b 100644
--- a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
+++ b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
@@ -37,6 +37,8 @@
+
+
@@ -49,6 +51,8 @@
+
+
@@ -76,6 +80,7 @@
+
diff --git a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
index 36cfeb77..6caf76b3 100644
--- a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
+++ b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
@@ -72,6 +72,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -137,6 +143,9 @@
tcg
+
+ tcg
+
tcg
@@ -151,6 +160,8 @@
+
+
diff --git a/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj b/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj
index d788e6ac..6e688605 100644
--- a/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj
+++ b/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj
@@ -37,6 +37,8 @@
+
+
@@ -49,6 +51,8 @@
+
+
@@ -76,6 +80,7 @@
+
diff --git a/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj.filters b/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj.filters
index 8656a124..1ecefe94 100644
--- a/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj.filters
+++ b/msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj.filters
@@ -69,6 +69,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -137,6 +143,9 @@
tcg
+
+ tcg
+
tcg
@@ -151,6 +160,8 @@
+
+
diff --git a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
index 2008c0b4..eafd9e92 100644
--- a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
+++ b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
@@ -36,6 +36,8 @@
+
+
@@ -48,6 +50,8 @@
+
+
@@ -72,6 +76,7 @@
+
diff --git a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
index cc15c82d..ded64259 100644
--- a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
+++ b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
@@ -33,6 +33,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -85,6 +91,8 @@
+
+
@@ -99,6 +107,9 @@
tcg
+
+ tcg
+
tcg
diff --git a/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj b/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj
index 1bc0fe02..93817f95 100644
--- a/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj
+++ b/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj
@@ -36,6 +36,8 @@
+
+
@@ -48,6 +50,8 @@
+
+
@@ -72,6 +76,7 @@
+
diff --git a/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj.filters b/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj.filters
index c8ee6310..dc7a7dc3 100644
--- a/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj.filters
+++ b/msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj.filters
@@ -63,6 +63,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -125,6 +131,9 @@
tcg
+
+ tcg
+
tcg
@@ -139,6 +148,8 @@
+
+
diff --git a/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj b/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj
index 4bb367c6..050c9414 100644
--- a/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj
+++ b/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj
@@ -26,6 +26,8 @@
+
+
@@ -43,6 +45,8 @@
+
+
@@ -55,6 +59,7 @@
+
diff --git a/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj.filters b/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj.filters
index 5e8bdaa6..3234adc0 100644
--- a/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj.filters
+++ b/msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj.filters
@@ -33,6 +33,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -74,6 +80,9 @@
tcg
+
+ tcg
+
tcg
@@ -88,6 +97,8 @@
+
+
diff --git a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj
index dd6ceeb5..6390de61 100644
--- a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj
+++ b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj
@@ -31,6 +31,8 @@
+
+
@@ -43,6 +45,8 @@
+
+
@@ -72,6 +76,7 @@
+
diff --git a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters
index 924cb64f..9c44aade 100644
--- a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters
+++ b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters
@@ -39,6 +39,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -70,6 +76,8 @@
+
+
@@ -84,6 +92,9 @@
tcg
+
+ tcg
+
tcg
diff --git a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj
index 80c94159..6e4df14c 100644
--- a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj
+++ b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj
@@ -31,6 +31,8 @@
+
+
@@ -43,6 +45,8 @@
+
+
@@ -72,6 +76,7 @@
+
diff --git a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters
index 3f47d1a1..04e554f2 100644
--- a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters
+++ b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters
@@ -36,6 +36,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -69,6 +75,8 @@
+
+
@@ -89,6 +97,9 @@
tcg
+
+ tcg
+
tcg
diff --git a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj
index 83be16c4..df8ce7af 100644
--- a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj
+++ b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj
@@ -31,6 +31,8 @@
+
+
@@ -43,6 +45,8 @@
+
+
@@ -72,6 +76,7 @@
+
diff --git a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters
index cb206215..5d26aeb6 100644
--- a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters
+++ b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters
@@ -39,6 +39,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -70,6 +76,8 @@
+
+
@@ -90,6 +98,9 @@
tcg
+
+ tcg
+
tcg
diff --git a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj
index 214453f9..fd6c846e 100644
--- a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj
+++ b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj
@@ -31,6 +31,8 @@
+
+
@@ -43,6 +45,8 @@
+
+
@@ -72,6 +76,7 @@
+
diff --git a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters
index 8a012a5e..8a41806f 100644
--- a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters
+++ b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters
@@ -39,6 +39,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -70,6 +76,8 @@
+
+
@@ -88,6 +96,9 @@
tcg
+
+ tcg
+
tcg
diff --git a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj
index cf516b2e..43e7f15c 100644
--- a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj
+++ b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj
@@ -26,6 +26,8 @@
+
+
@@ -43,6 +45,8 @@
+
+
@@ -66,6 +70,7 @@
+
diff --git a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters
index 1353b313..3703f4a4 100644
--- a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters
+++ b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters
@@ -36,6 +36,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -74,6 +80,9 @@
tcg
+
+ tcg
+
tcg
@@ -88,6 +97,8 @@
+
+
diff --git a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj
index fb562e75..25b8ed3d 100644
--- a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj
+++ b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj
@@ -26,6 +26,8 @@
+
+
@@ -43,6 +45,8 @@
+
+
@@ -67,6 +71,7 @@
+
diff --git a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters
index 2b81f5b5..a6cb8611 100644
--- a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters
+++ b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters
@@ -36,6 +36,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -107,6 +113,9 @@
tcg
+
+ tcg
+
tcg
@@ -122,6 +131,8 @@
+
+
diff --git a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj
index 06ba18ce..9a7a6ab2 100644
--- a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj
+++ b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj
@@ -36,6 +36,8 @@
+
+
@@ -48,6 +50,8 @@
+
+
@@ -80,6 +84,7 @@
+
diff --git a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters
index d197b431..f50eb0d8 100644
--- a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters
+++ b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters
@@ -36,6 +36,12 @@
tcg
+
+ tcg
+
+
+ tcg
+
tcg
@@ -88,6 +94,8 @@
+
+
@@ -159,6 +167,9 @@
tcg
+
+ tcg
+
tcg
diff --git a/qemu/Makefile.target b/qemu/Makefile.target
index c97a8c63..445d46f7 100644
--- a/qemu/Makefile.target
+++ b/qemu/Makefile.target
@@ -43,11 +43,11 @@ all: $(PROGS)
obj-y = exec.o translate-all.o cpu-exec.o
obj-y += translate-common.o
obj-y += cpu-exec-common.o
-obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o
+obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o
obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
obj-y += fpu/softfloat.o
obj-y += target/$(TARGET_BASE_ARCH)/
-obj-y += tcg-runtime.o
+obj-y += tcg-runtime.o tcg-runtime-gvec.o
obj-y += accel/
#########################################################
diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index b6926afe..e64b75ab 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_aarch64
#define dummy_func dummy_func_aarch64
#define dummy_section dummy_section_aarch64
+#define dup_const_impl dup_const_impl_aarch64
#define end_list end_list_aarch64
#define ensure_writable_pages ensure_writable_pages_aarch64
#define eq128 eq128_aarch64
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_aarch64
#define helper_get_r13_banked helper_get_r13_banked_aarch64
#define helper_get_user_reg helper_get_user_reg_aarch64
+#define helper_gvec_add8 helper_gvec_add8_aarch64
+#define helper_gvec_add16 helper_gvec_add16_aarch64
+#define helper_gvec_add32 helper_gvec_add32_aarch64
+#define helper_gvec_add64 helper_gvec_add64_aarch64
+#define helper_gvec_and helper_gvec_and_aarch64
+#define helper_gvec_andc helper_gvec_andc_aarch64
+#define helper_gvec_dup8 helper_gvec_dup8_aarch64
+#define helper_gvec_dup16 helper_gvec_dup16_aarch64
+#define helper_gvec_dup32 helper_gvec_dup32_aarch64
+#define helper_gvec_dup64 helper_gvec_dup64_aarch64
+#define helper_gvec_mov helper_gvec_mov_aarch64
+#define helper_gvec_neg8 helper_gvec_neg8_aarch64
+#define helper_gvec_neg16 helper_gvec_neg16_aarch64
+#define helper_gvec_neg32 helper_gvec_neg32_aarch64
+#define helper_gvec_neg64 helper_gvec_neg64_aarch64
+#define helper_gvec_not helper_gvec_not_aarch64
+#define helper_gvec_or helper_gvec_or_aarch64
+#define helper_gvec_orc helper_gvec_orc_aarch64
+#define helper_gvec_sub8 helper_gvec_sub8_aarch64
+#define helper_gvec_sub16 helper_gvec_sub16_aarch64
+#define helper_gvec_sub32 helper_gvec_sub32_aarch64
+#define helper_gvec_sub64 helper_gvec_sub64_aarch64
+#define helper_gvec_xor helper_gvec_xor_aarch64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_aarch64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_aarch64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_aarch64
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_aarch64
#define shortShift128Left shortShift128Left_aarch64
#define shortShift192Left shortShift192Left_aarch64
+#define simd_desc simd_desc_aarch64
#define simple_mpu_ap_bits simple_mpu_ap_bits_aarch64
#define size_code_gen_buffer size_code_gen_buffer_aarch64
#define softmmu_lock_user softmmu_lock_user_aarch64
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_aarch64
#define tcg_exec_all tcg_exec_all_aarch64
#define tcg_exec_init tcg_exec_init_aarch64
+#define tcg_expand_vec_op tcg_expand_vec_op_aarch64
#define tcg_find_helper tcg_find_helper_aarch64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_aarch64
#define tcg_func_start tcg_func_start_aarch64
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_aarch64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_aarch64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_aarch64
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_aarch64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_aarch64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_aarch64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_aarch64
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_aarch64
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_aarch64
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_aarch64
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64
+#define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64
+#define tcg_gen_gvec_and tcg_gen_gvec_and_aarch64
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_aarch64
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_aarch64
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_aarch64
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_aarch64
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_aarch64
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_aarch64
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_aarch64
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_aarch64
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_aarch64
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_aarch64
+#define tcg_gen_gvec_not tcg_gen_gvec_not_aarch64
+#define tcg_gen_gvec_or tcg_gen_gvec_or_aarch64
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64
#define tcg_gen_insn_start tcg_gen_insn_start_aarch64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_aarch64
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_aarch64
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_aarch64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64
#define tcg_gen_xor_vec tcg_gen_xor_vec_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index 40dd0e8a..5a4e8ea1 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_aarch64eb
#define dummy_func dummy_func_aarch64eb
#define dummy_section dummy_section_aarch64eb
+#define dup_const_impl dup_const_impl_aarch64eb
#define end_list end_list_aarch64eb
#define ensure_writable_pages ensure_writable_pages_aarch64eb
#define eq128 eq128_aarch64eb
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_aarch64eb
#define helper_get_r13_banked helper_get_r13_banked_aarch64eb
#define helper_get_user_reg helper_get_user_reg_aarch64eb
+#define helper_gvec_add8 helper_gvec_add8_aarch64eb
+#define helper_gvec_add16 helper_gvec_add16_aarch64eb
+#define helper_gvec_add32 helper_gvec_add32_aarch64eb
+#define helper_gvec_add64 helper_gvec_add64_aarch64eb
+#define helper_gvec_and helper_gvec_and_aarch64eb
+#define helper_gvec_andc helper_gvec_andc_aarch64eb
+#define helper_gvec_dup8 helper_gvec_dup8_aarch64eb
+#define helper_gvec_dup16 helper_gvec_dup16_aarch64eb
+#define helper_gvec_dup32 helper_gvec_dup32_aarch64eb
+#define helper_gvec_dup64 helper_gvec_dup64_aarch64eb
+#define helper_gvec_mov helper_gvec_mov_aarch64eb
+#define helper_gvec_neg8 helper_gvec_neg8_aarch64eb
+#define helper_gvec_neg16 helper_gvec_neg16_aarch64eb
+#define helper_gvec_neg32 helper_gvec_neg32_aarch64eb
+#define helper_gvec_neg64 helper_gvec_neg64_aarch64eb
+#define helper_gvec_not helper_gvec_not_aarch64eb
+#define helper_gvec_or helper_gvec_or_aarch64eb
+#define helper_gvec_orc helper_gvec_orc_aarch64eb
+#define helper_gvec_sub8 helper_gvec_sub8_aarch64eb
+#define helper_gvec_sub16 helper_gvec_sub16_aarch64eb
+#define helper_gvec_sub32 helper_gvec_sub32_aarch64eb
+#define helper_gvec_sub64 helper_gvec_sub64_aarch64eb
+#define helper_gvec_xor helper_gvec_xor_aarch64eb
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_aarch64eb
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_aarch64eb
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_aarch64eb
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_aarch64eb
#define shortShift128Left shortShift128Left_aarch64eb
#define shortShift192Left shortShift192Left_aarch64eb
+#define simd_desc simd_desc_aarch64eb
#define simple_mpu_ap_bits simple_mpu_ap_bits_aarch64eb
#define size_code_gen_buffer size_code_gen_buffer_aarch64eb
#define softmmu_lock_user softmmu_lock_user_aarch64eb
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_aarch64eb
#define tcg_exec_all tcg_exec_all_aarch64eb
#define tcg_exec_init tcg_exec_init_aarch64eb
+#define tcg_expand_vec_op tcg_expand_vec_op_aarch64eb
#define tcg_find_helper tcg_find_helper_aarch64eb
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_aarch64eb
#define tcg_func_start tcg_func_start_aarch64eb
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_aarch64eb
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_aarch64eb
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_aarch64eb
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_aarch64eb
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_aarch64eb
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_aarch64eb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64eb
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64eb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64eb
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_aarch64eb
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64eb
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64eb
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64eb
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_aarch64eb
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_aarch64eb
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_aarch64eb
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64eb
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64eb
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64eb
+#define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64eb
+#define tcg_gen_gvec_and tcg_gen_gvec_and_aarch64eb
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_aarch64eb
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_aarch64eb
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_aarch64eb
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_aarch64eb
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_aarch64eb
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_aarch64eb
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_aarch64eb
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_aarch64eb
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_aarch64eb
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_aarch64eb
+#define tcg_gen_gvec_not tcg_gen_gvec_not_aarch64eb
+#define tcg_gen_gvec_or tcg_gen_gvec_or_aarch64eb
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64eb
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64eb
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64eb
#define tcg_gen_insn_start tcg_gen_insn_start_aarch64eb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64eb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64eb
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64eb
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64eb
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64eb
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64eb
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64eb
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64eb
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_aarch64eb
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_aarch64eb
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_aarch64eb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64eb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64eb
#define tcg_gen_xor_vec tcg_gen_xor_vec_aarch64eb
diff --git a/qemu/arm.h b/qemu/arm.h
index 65d548cd..caf4bc3c 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_arm
#define dummy_func dummy_func_arm
#define dummy_section dummy_section_arm
+#define dup_const_impl dup_const_impl_arm
#define end_list end_list_arm
#define ensure_writable_pages ensure_writable_pages_arm
#define eq128 eq128_arm
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_arm
#define helper_get_r13_banked helper_get_r13_banked_arm
#define helper_get_user_reg helper_get_user_reg_arm
+#define helper_gvec_add8 helper_gvec_add8_arm
+#define helper_gvec_add16 helper_gvec_add16_arm
+#define helper_gvec_add32 helper_gvec_add32_arm
+#define helper_gvec_add64 helper_gvec_add64_arm
+#define helper_gvec_and helper_gvec_and_arm
+#define helper_gvec_andc helper_gvec_andc_arm
+#define helper_gvec_dup8 helper_gvec_dup8_arm
+#define helper_gvec_dup16 helper_gvec_dup16_arm
+#define helper_gvec_dup32 helper_gvec_dup32_arm
+#define helper_gvec_dup64 helper_gvec_dup64_arm
+#define helper_gvec_mov helper_gvec_mov_arm
+#define helper_gvec_neg8 helper_gvec_neg8_arm
+#define helper_gvec_neg16 helper_gvec_neg16_arm
+#define helper_gvec_neg32 helper_gvec_neg32_arm
+#define helper_gvec_neg64 helper_gvec_neg64_arm
+#define helper_gvec_not helper_gvec_not_arm
+#define helper_gvec_or helper_gvec_or_arm
+#define helper_gvec_orc helper_gvec_orc_arm
+#define helper_gvec_sub8 helper_gvec_sub8_arm
+#define helper_gvec_sub16 helper_gvec_sub16_arm
+#define helper_gvec_sub32 helper_gvec_sub32_arm
+#define helper_gvec_sub64 helper_gvec_sub64_arm
+#define helper_gvec_xor helper_gvec_xor_arm
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_arm
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_arm
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_arm
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_arm
#define shortShift128Left shortShift128Left_arm
#define shortShift192Left shortShift192Left_arm
+#define simd_desc simd_desc_arm
#define simple_mpu_ap_bits simple_mpu_ap_bits_arm
#define size_code_gen_buffer size_code_gen_buffer_arm
#define softmmu_lock_user softmmu_lock_user_arm
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_arm
#define tcg_exec_all tcg_exec_all_arm
#define tcg_exec_init tcg_exec_init_arm
+#define tcg_expand_vec_op tcg_expand_vec_op_arm
#define tcg_find_helper tcg_find_helper_arm
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_arm
#define tcg_func_start tcg_func_start_arm
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_arm
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_arm
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_arm
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_arm
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_arm
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_arm
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_arm
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_arm
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm
#define tcg_gen_goto_tb tcg_gen_goto_tb_arm
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_arm
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_arm
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_arm
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_arm
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_arm
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_arm
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_arm
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_arm
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_arm
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_arm
+#define tcg_gen_gvec_add tcg_gen_gvec_add_arm
+#define tcg_gen_gvec_and tcg_gen_gvec_and_arm
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_arm
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_arm
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_arm
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_arm
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_arm
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_arm
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_arm
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_arm
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_arm
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_arm
+#define tcg_gen_gvec_not tcg_gen_gvec_not_arm
+#define tcg_gen_gvec_or tcg_gen_gvec_or_arm
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_arm
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_arm
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_arm
#define tcg_gen_insn_start tcg_gen_insn_start_arm
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_arm
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_arm
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm
#define tcg_gen_subi_i32 tcg_gen_subi_i32_arm
#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_arm
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_arm
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_arm
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_arm
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_arm
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_arm
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_arm
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_arm
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_arm
#define tcg_gen_xor_i32 tcg_gen_xor_i32_arm
#define tcg_gen_xor_i64 tcg_gen_xor_i64_arm
#define tcg_gen_xor_vec tcg_gen_xor_vec_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index 23ca0dd6..105e56ec 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_armeb
#define dummy_func dummy_func_armeb
#define dummy_section dummy_section_armeb
+#define dup_const_impl dup_const_impl_armeb
#define end_list end_list_armeb
#define ensure_writable_pages ensure_writable_pages_armeb
#define eq128 eq128_armeb
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_armeb
#define helper_get_r13_banked helper_get_r13_banked_armeb
#define helper_get_user_reg helper_get_user_reg_armeb
+#define helper_gvec_add8 helper_gvec_add8_armeb
+#define helper_gvec_add16 helper_gvec_add16_armeb
+#define helper_gvec_add32 helper_gvec_add32_armeb
+#define helper_gvec_add64 helper_gvec_add64_armeb
+#define helper_gvec_and helper_gvec_and_armeb
+#define helper_gvec_andc helper_gvec_andc_armeb
+#define helper_gvec_dup8 helper_gvec_dup8_armeb
+#define helper_gvec_dup16 helper_gvec_dup16_armeb
+#define helper_gvec_dup32 helper_gvec_dup32_armeb
+#define helper_gvec_dup64 helper_gvec_dup64_armeb
+#define helper_gvec_mov helper_gvec_mov_armeb
+#define helper_gvec_neg8 helper_gvec_neg8_armeb
+#define helper_gvec_neg16 helper_gvec_neg16_armeb
+#define helper_gvec_neg32 helper_gvec_neg32_armeb
+#define helper_gvec_neg64 helper_gvec_neg64_armeb
+#define helper_gvec_not helper_gvec_not_armeb
+#define helper_gvec_or helper_gvec_or_armeb
+#define helper_gvec_orc helper_gvec_orc_armeb
+#define helper_gvec_sub8 helper_gvec_sub8_armeb
+#define helper_gvec_sub16 helper_gvec_sub16_armeb
+#define helper_gvec_sub32 helper_gvec_sub32_armeb
+#define helper_gvec_sub64 helper_gvec_sub64_armeb
+#define helper_gvec_xor helper_gvec_xor_armeb
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_armeb
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_armeb
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_armeb
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_armeb
#define shortShift128Left shortShift128Left_armeb
#define shortShift192Left shortShift192Left_armeb
+#define simd_desc simd_desc_armeb
#define simple_mpu_ap_bits simple_mpu_ap_bits_armeb
#define size_code_gen_buffer size_code_gen_buffer_armeb
#define softmmu_lock_user softmmu_lock_user_armeb
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_armeb
#define tcg_exec_all tcg_exec_all_armeb
#define tcg_exec_init tcg_exec_init_armeb
+#define tcg_expand_vec_op tcg_expand_vec_op_armeb
#define tcg_find_helper tcg_find_helper_armeb
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_armeb
#define tcg_func_start tcg_func_start_armeb
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_armeb
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_armeb
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_armeb
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_armeb
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_armeb
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_armeb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_armeb
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_armeb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb
#define tcg_gen_goto_tb tcg_gen_goto_tb_armeb
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_armeb
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_armeb
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_armeb
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_armeb
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_armeb
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_armeb
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_armeb
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_armeb
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_armeb
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_armeb
+#define tcg_gen_gvec_add tcg_gen_gvec_add_armeb
+#define tcg_gen_gvec_and tcg_gen_gvec_and_armeb
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_armeb
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_armeb
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_armeb
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_armeb
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_armeb
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_armeb
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_armeb
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_armeb
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_armeb
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_armeb
+#define tcg_gen_gvec_not tcg_gen_gvec_not_armeb
+#define tcg_gen_gvec_or tcg_gen_gvec_or_armeb
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_armeb
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_armeb
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_armeb
#define tcg_gen_insn_start tcg_gen_insn_start_armeb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_armeb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_armeb
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_armeb
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_armeb
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_armeb
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_armeb
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_armeb
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_armeb
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_armeb
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_armeb
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_armeb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_armeb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_armeb
#define tcg_gen_xor_vec tcg_gen_xor_vec_armeb
diff --git a/qemu/configure b/qemu/configure
index 4b336af9..33e7c224 100755
--- a/qemu/configure
+++ b/qemu/configure
@@ -1086,6 +1086,50 @@ if compile_prog "" "" ; then
int128=yes
fi
+########################################
+# See if 16-byte vector operations are supported.
+# Even without a vector unit the compiler may expand these.
+# There is a bug in old GCC for PPC that crashes here.
+# Unfortunately it's the system compiler for Centos 7.
+
+cat > $TMPC << EOF
+typedef unsigned char U1 __attribute__((vector_size(16)));
+typedef unsigned short U2 __attribute__((vector_size(16)));
+typedef unsigned int U4 __attribute__((vector_size(16)));
+typedef unsigned long long U8 __attribute__((vector_size(16)));
+typedef signed char S1 __attribute__((vector_size(16)));
+typedef signed short S2 __attribute__((vector_size(16)));
+typedef signed int S4 __attribute__((vector_size(16)));
+typedef signed long long S8 __attribute__((vector_size(16)));
+static U1 a1, b1;
+static U2 a2, b2;
+static U4 a4, b4;
+static U8 a8, b8;
+static S1 c1;
+static S2 c2;
+static S4 c4;
+static S8 c8;
+static int i;
+int main(void)
+{
+ a1 += b1; a2 += b2; a4 += b4; a8 += b8;
+ a1 -= b1; a2 -= b2; a4 -= b4; a8 -= b8;
+ a1 *= b1; a2 *= b2; a4 *= b4; a8 *= b8;
+ a1 &= b1; a2 &= b2; a4 &= b4; a8 &= b8;
+ a1 |= b1; a2 |= b2; a4 |= b4; a8 |= b8;
+ a1 ^= b1; a2 ^= b2; a4 ^= b4; a8 ^= b8;
+ a1 <<= i; a2 <<= i; a4 <<= i; a8 <<= i;
+ a1 >>= i; a2 >>= i; a4 >>= i; a8 >>= i;
+ c1 >>= i; c2 >>= i; c4 >>= i; c8 >>= i;
+ return 0;
+}
+EOF
+
+vector16=no
+if compile_prog "" "" ; then
+ vector16=yes
+fi
+
#########################################
# See if 128-bit atomic operations are supported.
@@ -1299,6 +1343,10 @@ if test "$atomic64" = "yes" ; then
echo "CONFIG_ATOMIC64=y" >> $config_host_mak
fi
+if test "$vector16" = "yes" ; then
+ echo "CONFIG_VECTOR16=y" >> $config_host_mak
+fi
+
if test "$tcg_interpreter" = "yes"; then
QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/tci $QEMU_INCLUDES"
elif test "$ARCH" = "sparc64" ; then
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 49a42e1e..8725bc7c 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -407,6 +407,7 @@ symbols = (
'dummy_c15_cp_reginfo',
'dummy_func',
'dummy_section',
+ 'dup_const_impl',
'end_list',
'ensure_writable_pages',
'eq128',
@@ -1614,6 +1615,29 @@ symbols = (
'helper_get_cp_reg64',
'helper_get_r13_banked',
'helper_get_user_reg',
+ 'helper_gvec_add8',
+ 'helper_gvec_add16',
+ 'helper_gvec_add32',
+ 'helper_gvec_add64',
+ 'helper_gvec_and',
+ 'helper_gvec_andc',
+ 'helper_gvec_dup8',
+ 'helper_gvec_dup16',
+ 'helper_gvec_dup32',
+ 'helper_gvec_dup64',
+ 'helper_gvec_mov',
+ 'helper_gvec_neg8',
+ 'helper_gvec_neg16',
+ 'helper_gvec_neg32',
+ 'helper_gvec_neg64',
+ 'helper_gvec_not',
+ 'helper_gvec_or',
+ 'helper_gvec_orc',
+ 'helper_gvec_sub8',
+ 'helper_gvec_sub16',
+ 'helper_gvec_sub32',
+ 'helper_gvec_sub64',
+ 'helper_gvec_xor',
'helper_iwmmxt_addcb',
'helper_iwmmxt_addcl',
'helper_iwmmxt_addcw',
@@ -2836,6 +2860,7 @@ symbols = (
'shifter_out_im',
'shortShift128Left',
'shortShift192Left',
+ 'simd_desc',
'simple_mpu_ap_bits',
'size_code_gen_buffer',
'softmmu_lock_user',
@@ -2991,6 +3016,7 @@ symbols = (
'tcg_enabled',
'tcg_exec_all',
'tcg_exec_init',
+ 'tcg_expand_vec_op',
'tcg_find_helper',
'tcg_flush_softmmu_tlb',
'tcg_func_start',
@@ -3068,6 +3094,7 @@ symbols = (
'tcg_gen_dup16i_vec',
'tcg_gen_dup32i_vec',
'tcg_gen_dup64i_vec',
+ 'tcg_gen_dupi_vec',
'tcg_gen_dup_i32_vec',
'tcg_gen_dup_i64_vec',
'tcg_gen_eqv_i32',
@@ -3092,6 +3119,33 @@ symbols = (
'tcg_gen_extrl_i64_i32',
'tcg_gen_extu_i32_i64',
'tcg_gen_goto_tb',
+ 'tcg_gen_gvec_2',
+ 'tcg_gen_gvec_2_ool',
+ 'tcg_gen_gvec_2_ptr',
+ 'tcg_gen_gvec_3',
+ 'tcg_gen_gvec_3_ool',
+ 'tcg_gen_gvec_3_ptr',
+ 'tcg_gen_gvec_4',
+ 'tcg_gen_gvec_4_ool',
+ 'tcg_gen_gvec_4_ptr',
+ 'tcg_gen_gvec_5_ool',
+ 'tcg_gen_gvec_add',
+ 'tcg_gen_gvec_and',
+ 'tcg_gen_gvec_andc',
+ 'tcg_gen_gvec_dup8i',
+ 'tcg_gen_gvec_dup16i',
+ 'tcg_gen_gvec_dup32i',
+ 'tcg_gen_gvec_dup64i',
+ 'tcg_gen_gvec_dup_i32',
+ 'tcg_gen_gvec_dup_i64',
+ 'tcg_gen_gvec_dup_mem',
+ 'tcg_gen_gvec_mov',
+ 'tcg_gen_gvec_neg',
+ 'tcg_gen_gvec_not',
+ 'tcg_gen_gvec_or',
+ 'tcg_gen_gvec_orc',
+ 'tcg_gen_gvec_sub',
+ 'tcg_gen_gvec_xor',
'tcg_gen_insn_start',
'tcg_gen_ld16s_i64',
'tcg_gen_ld16u_i64',
@@ -3211,6 +3265,15 @@ symbols = (
'tcg_gen_subfi_i64',
'tcg_gen_subi_i32',
'tcg_gen_subi_i64',
+ 'tcg_gen_vec_add8_i64',
+ 'tcg_gen_vec_add16_i64',
+ 'tcg_gen_vec_add32_i64',
+ 'tcg_gen_vec_neg8_i64',
+ 'tcg_gen_vec_neg16_i64',
+ 'tcg_gen_vec_neg32_i64',
+ 'tcg_gen_vec_sub8_i64',
+ 'tcg_gen_vec_sub16_i64',
+ 'tcg_gen_vec_sub32_i64',
'tcg_gen_xor_i32',
'tcg_gen_xor_i64',
'tcg_gen_xor_vec',
diff --git a/qemu/m68k.h b/qemu/m68k.h
index e67ec6cd..187b47bf 100644
--- a/qemu/m68k.h
+++ b/qemu/m68k.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_m68k
#define dummy_func dummy_func_m68k
#define dummy_section dummy_section_m68k
+#define dup_const_impl dup_const_impl_m68k
#define end_list end_list_m68k
#define ensure_writable_pages ensure_writable_pages_m68k
#define eq128 eq128_m68k
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_m68k
#define helper_get_r13_banked helper_get_r13_banked_m68k
#define helper_get_user_reg helper_get_user_reg_m68k
+#define helper_gvec_add8 helper_gvec_add8_m68k
+#define helper_gvec_add16 helper_gvec_add16_m68k
+#define helper_gvec_add32 helper_gvec_add32_m68k
+#define helper_gvec_add64 helper_gvec_add64_m68k
+#define helper_gvec_and helper_gvec_and_m68k
+#define helper_gvec_andc helper_gvec_andc_m68k
+#define helper_gvec_dup8 helper_gvec_dup8_m68k
+#define helper_gvec_dup16 helper_gvec_dup16_m68k
+#define helper_gvec_dup32 helper_gvec_dup32_m68k
+#define helper_gvec_dup64 helper_gvec_dup64_m68k
+#define helper_gvec_mov helper_gvec_mov_m68k
+#define helper_gvec_neg8 helper_gvec_neg8_m68k
+#define helper_gvec_neg16 helper_gvec_neg16_m68k
+#define helper_gvec_neg32 helper_gvec_neg32_m68k
+#define helper_gvec_neg64 helper_gvec_neg64_m68k
+#define helper_gvec_not helper_gvec_not_m68k
+#define helper_gvec_or helper_gvec_or_m68k
+#define helper_gvec_orc helper_gvec_orc_m68k
+#define helper_gvec_sub8 helper_gvec_sub8_m68k
+#define helper_gvec_sub16 helper_gvec_sub16_m68k
+#define helper_gvec_sub32 helper_gvec_sub32_m68k
+#define helper_gvec_sub64 helper_gvec_sub64_m68k
+#define helper_gvec_xor helper_gvec_xor_m68k
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_m68k
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_m68k
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_m68k
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_m68k
#define shortShift128Left shortShift128Left_m68k
#define shortShift192Left shortShift192Left_m68k
+#define simd_desc simd_desc_m68k
#define simple_mpu_ap_bits simple_mpu_ap_bits_m68k
#define size_code_gen_buffer size_code_gen_buffer_m68k
#define softmmu_lock_user softmmu_lock_user_m68k
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_m68k
#define tcg_exec_all tcg_exec_all_m68k
#define tcg_exec_init tcg_exec_init_m68k
+#define tcg_expand_vec_op tcg_expand_vec_op_m68k
#define tcg_find_helper tcg_find_helper_m68k
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_m68k
#define tcg_func_start tcg_func_start_m68k
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_m68k
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_m68k
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_m68k
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_m68k
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_m68k
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_m68k
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_m68k
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_m68k
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k
#define tcg_gen_goto_tb tcg_gen_goto_tb_m68k
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_m68k
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_m68k
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_m68k
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_m68k
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_m68k
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_m68k
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_m68k
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_m68k
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_m68k
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_m68k
+#define tcg_gen_gvec_add tcg_gen_gvec_add_m68k
+#define tcg_gen_gvec_and tcg_gen_gvec_and_m68k
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_m68k
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_m68k
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_m68k
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_m68k
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_m68k
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_m68k
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_m68k
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_m68k
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_m68k
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_m68k
+#define tcg_gen_gvec_not tcg_gen_gvec_not_m68k
+#define tcg_gen_gvec_or tcg_gen_gvec_or_m68k
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_m68k
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_m68k
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_m68k
#define tcg_gen_insn_start tcg_gen_insn_start_m68k
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_m68k
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_m68k
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k
#define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k
#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_m68k
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_m68k
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_m68k
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_m68k
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_m68k
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_m68k
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_m68k
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_m68k
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_m68k
#define tcg_gen_xor_i32 tcg_gen_xor_i32_m68k
#define tcg_gen_xor_i64 tcg_gen_xor_i64_m68k
#define tcg_gen_xor_vec tcg_gen_xor_vec_m68k
diff --git a/qemu/mips.h b/qemu/mips.h
index 8c7a0bcd..1ee3baa8 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mips
#define dummy_func dummy_func_mips
#define dummy_section dummy_section_mips
+#define dup_const_impl dup_const_impl_mips
#define end_list end_list_mips
#define ensure_writable_pages ensure_writable_pages_mips
#define eq128 eq128_mips
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mips
#define helper_get_r13_banked helper_get_r13_banked_mips
#define helper_get_user_reg helper_get_user_reg_mips
+#define helper_gvec_add8 helper_gvec_add8_mips
+#define helper_gvec_add16 helper_gvec_add16_mips
+#define helper_gvec_add32 helper_gvec_add32_mips
+#define helper_gvec_add64 helper_gvec_add64_mips
+#define helper_gvec_and helper_gvec_and_mips
+#define helper_gvec_andc helper_gvec_andc_mips
+#define helper_gvec_dup8 helper_gvec_dup8_mips
+#define helper_gvec_dup16 helper_gvec_dup16_mips
+#define helper_gvec_dup32 helper_gvec_dup32_mips
+#define helper_gvec_dup64 helper_gvec_dup64_mips
+#define helper_gvec_mov helper_gvec_mov_mips
+#define helper_gvec_neg8 helper_gvec_neg8_mips
+#define helper_gvec_neg16 helper_gvec_neg16_mips
+#define helper_gvec_neg32 helper_gvec_neg32_mips
+#define helper_gvec_neg64 helper_gvec_neg64_mips
+#define helper_gvec_not helper_gvec_not_mips
+#define helper_gvec_or helper_gvec_or_mips
+#define helper_gvec_orc helper_gvec_orc_mips
+#define helper_gvec_sub8 helper_gvec_sub8_mips
+#define helper_gvec_sub16 helper_gvec_sub16_mips
+#define helper_gvec_sub32 helper_gvec_sub32_mips
+#define helper_gvec_sub64 helper_gvec_sub64_mips
+#define helper_gvec_xor helper_gvec_xor_mips
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mips
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mips
#define shortShift128Left shortShift128Left_mips
#define shortShift192Left shortShift192Left_mips
+#define simd_desc simd_desc_mips
#define simple_mpu_ap_bits simple_mpu_ap_bits_mips
#define size_code_gen_buffer size_code_gen_buffer_mips
#define softmmu_lock_user softmmu_lock_user_mips
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mips
#define tcg_exec_all tcg_exec_all_mips
#define tcg_exec_init tcg_exec_init_mips
+#define tcg_expand_vec_op tcg_expand_vec_op_mips
#define tcg_find_helper tcg_find_helper_mips
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mips
#define tcg_func_start tcg_func_start_mips
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mips
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_mips
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips
+#define tcg_gen_gvec_add tcg_gen_gvec_add_mips
+#define tcg_gen_gvec_and tcg_gen_gvec_and_mips
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mips
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mips
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mips
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mips
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mips
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mips
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mips
+#define tcg_gen_gvec_not tcg_gen_gvec_not_mips
+#define tcg_gen_gvec_or tcg_gen_gvec_or_mips
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips
#define tcg_gen_insn_start tcg_gen_insn_start_mips
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index 85a1f4bb..bf9f01da 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mips64
#define dummy_func dummy_func_mips64
#define dummy_section dummy_section_mips64
+#define dup_const_impl dup_const_impl_mips64
#define end_list end_list_mips64
#define ensure_writable_pages ensure_writable_pages_mips64
#define eq128 eq128_mips64
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mips64
#define helper_get_r13_banked helper_get_r13_banked_mips64
#define helper_get_user_reg helper_get_user_reg_mips64
+#define helper_gvec_add8 helper_gvec_add8_mips64
+#define helper_gvec_add16 helper_gvec_add16_mips64
+#define helper_gvec_add32 helper_gvec_add32_mips64
+#define helper_gvec_add64 helper_gvec_add64_mips64
+#define helper_gvec_and helper_gvec_and_mips64
+#define helper_gvec_andc helper_gvec_andc_mips64
+#define helper_gvec_dup8 helper_gvec_dup8_mips64
+#define helper_gvec_dup16 helper_gvec_dup16_mips64
+#define helper_gvec_dup32 helper_gvec_dup32_mips64
+#define helper_gvec_dup64 helper_gvec_dup64_mips64
+#define helper_gvec_mov helper_gvec_mov_mips64
+#define helper_gvec_neg8 helper_gvec_neg8_mips64
+#define helper_gvec_neg16 helper_gvec_neg16_mips64
+#define helper_gvec_neg32 helper_gvec_neg32_mips64
+#define helper_gvec_neg64 helper_gvec_neg64_mips64
+#define helper_gvec_not helper_gvec_not_mips64
+#define helper_gvec_or helper_gvec_or_mips64
+#define helper_gvec_orc helper_gvec_orc_mips64
+#define helper_gvec_sub8 helper_gvec_sub8_mips64
+#define helper_gvec_sub16 helper_gvec_sub16_mips64
+#define helper_gvec_sub32 helper_gvec_sub32_mips64
+#define helper_gvec_sub64 helper_gvec_sub64_mips64
+#define helper_gvec_xor helper_gvec_xor_mips64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mips64
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mips64
#define shortShift128Left shortShift128Left_mips64
#define shortShift192Left shortShift192Left_mips64
+#define simd_desc simd_desc_mips64
#define simple_mpu_ap_bits simple_mpu_ap_bits_mips64
#define size_code_gen_buffer size_code_gen_buffer_mips64
#define softmmu_lock_user softmmu_lock_user_mips64
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mips64
#define tcg_exec_all tcg_exec_all_mips64
#define tcg_exec_init tcg_exec_init_mips64
+#define tcg_expand_vec_op tcg_expand_vec_op_mips64
#define tcg_find_helper tcg_find_helper_mips64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mips64
#define tcg_func_start tcg_func_start_mips64
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips64
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mips64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips64
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips64
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips64
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_mips64
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64
+#define tcg_gen_gvec_add tcg_gen_gvec_add_mips64
+#define tcg_gen_gvec_and tcg_gen_gvec_and_mips64
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips64
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips64
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips64
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mips64
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mips64
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mips64
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mips64
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mips64
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mips64
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mips64
+#define tcg_gen_gvec_not tcg_gen_gvec_not_mips64
+#define tcg_gen_gvec_or tcg_gen_gvec_or_mips64
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64
#define tcg_gen_insn_start tcg_gen_insn_start_mips64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips64
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips64
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 0252d9dd..bf08afbe 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mips64el
#define dummy_func dummy_func_mips64el
#define dummy_section dummy_section_mips64el
+#define dup_const_impl dup_const_impl_mips64el
#define end_list end_list_mips64el
#define ensure_writable_pages ensure_writable_pages_mips64el
#define eq128 eq128_mips64el
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mips64el
#define helper_get_r13_banked helper_get_r13_banked_mips64el
#define helper_get_user_reg helper_get_user_reg_mips64el
+#define helper_gvec_add8 helper_gvec_add8_mips64el
+#define helper_gvec_add16 helper_gvec_add16_mips64el
+#define helper_gvec_add32 helper_gvec_add32_mips64el
+#define helper_gvec_add64 helper_gvec_add64_mips64el
+#define helper_gvec_and helper_gvec_and_mips64el
+#define helper_gvec_andc helper_gvec_andc_mips64el
+#define helper_gvec_dup8 helper_gvec_dup8_mips64el
+#define helper_gvec_dup16 helper_gvec_dup16_mips64el
+#define helper_gvec_dup32 helper_gvec_dup32_mips64el
+#define helper_gvec_dup64 helper_gvec_dup64_mips64el
+#define helper_gvec_mov helper_gvec_mov_mips64el
+#define helper_gvec_neg8 helper_gvec_neg8_mips64el
+#define helper_gvec_neg16 helper_gvec_neg16_mips64el
+#define helper_gvec_neg32 helper_gvec_neg32_mips64el
+#define helper_gvec_neg64 helper_gvec_neg64_mips64el
+#define helper_gvec_not helper_gvec_not_mips64el
+#define helper_gvec_or helper_gvec_or_mips64el
+#define helper_gvec_orc helper_gvec_orc_mips64el
+#define helper_gvec_sub8 helper_gvec_sub8_mips64el
+#define helper_gvec_sub16 helper_gvec_sub16_mips64el
+#define helper_gvec_sub32 helper_gvec_sub32_mips64el
+#define helper_gvec_sub64 helper_gvec_sub64_mips64el
+#define helper_gvec_xor helper_gvec_xor_mips64el
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips64el
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips64el
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mips64el
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mips64el
#define shortShift128Left shortShift128Left_mips64el
#define shortShift192Left shortShift192Left_mips64el
+#define simd_desc simd_desc_mips64el
#define simple_mpu_ap_bits simple_mpu_ap_bits_mips64el
#define size_code_gen_buffer size_code_gen_buffer_mips64el
#define softmmu_lock_user softmmu_lock_user_mips64el
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mips64el
#define tcg_exec_all tcg_exec_all_mips64el
#define tcg_exec_init tcg_exec_init_mips64el
+#define tcg_expand_vec_op tcg_expand_vec_op_mips64el
#define tcg_find_helper tcg_find_helper_mips64el
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mips64el
#define tcg_func_start tcg_func_start_mips64el
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips64el
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips64el
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips64el
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mips64el
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips64el
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips64el
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64el
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64el
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64el
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips64el
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64el
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64el
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64el
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips64el
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips64el
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_mips64el
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64el
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64el
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64el
+#define tcg_gen_gvec_add tcg_gen_gvec_add_mips64el
+#define tcg_gen_gvec_and tcg_gen_gvec_and_mips64el
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips64el
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips64el
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips64el
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mips64el
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mips64el
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mips64el
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mips64el
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mips64el
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mips64el
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mips64el
+#define tcg_gen_gvec_not tcg_gen_gvec_not_mips64el
+#define tcg_gen_gvec_or tcg_gen_gvec_or_mips64el
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64el
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64el
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64el
#define tcg_gen_insn_start tcg_gen_insn_start_mips64el
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64el
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64el
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64el
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64el
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64el
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64el
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64el
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64el
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips64el
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips64el
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips64el
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64el
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64el
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index eb5f75e1..e5a214dc 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_mipsel
#define dummy_func dummy_func_mipsel
#define dummy_section dummy_section_mipsel
+#define dup_const_impl dup_const_impl_mipsel
#define end_list end_list_mipsel
#define ensure_writable_pages ensure_writable_pages_mipsel
#define eq128 eq128_mipsel
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_mipsel
#define helper_get_r13_banked helper_get_r13_banked_mipsel
#define helper_get_user_reg helper_get_user_reg_mipsel
+#define helper_gvec_add8 helper_gvec_add8_mipsel
+#define helper_gvec_add16 helper_gvec_add16_mipsel
+#define helper_gvec_add32 helper_gvec_add32_mipsel
+#define helper_gvec_add64 helper_gvec_add64_mipsel
+#define helper_gvec_and helper_gvec_and_mipsel
+#define helper_gvec_andc helper_gvec_andc_mipsel
+#define helper_gvec_dup8 helper_gvec_dup8_mipsel
+#define helper_gvec_dup16 helper_gvec_dup16_mipsel
+#define helper_gvec_dup32 helper_gvec_dup32_mipsel
+#define helper_gvec_dup64 helper_gvec_dup64_mipsel
+#define helper_gvec_mov helper_gvec_mov_mipsel
+#define helper_gvec_neg8 helper_gvec_neg8_mipsel
+#define helper_gvec_neg16 helper_gvec_neg16_mipsel
+#define helper_gvec_neg32 helper_gvec_neg32_mipsel
+#define helper_gvec_neg64 helper_gvec_neg64_mipsel
+#define helper_gvec_not helper_gvec_not_mipsel
+#define helper_gvec_or helper_gvec_or_mipsel
+#define helper_gvec_orc helper_gvec_orc_mipsel
+#define helper_gvec_sub8 helper_gvec_sub8_mipsel
+#define helper_gvec_sub16 helper_gvec_sub16_mipsel
+#define helper_gvec_sub32 helper_gvec_sub32_mipsel
+#define helper_gvec_sub64 helper_gvec_sub64_mipsel
+#define helper_gvec_xor helper_gvec_xor_mipsel
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mipsel
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mipsel
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_mipsel
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_mipsel
#define shortShift128Left shortShift128Left_mipsel
#define shortShift192Left shortShift192Left_mipsel
+#define simd_desc simd_desc_mipsel
#define simple_mpu_ap_bits simple_mpu_ap_bits_mipsel
#define size_code_gen_buffer size_code_gen_buffer_mipsel
#define softmmu_lock_user softmmu_lock_user_mipsel
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_mipsel
#define tcg_exec_all tcg_exec_all_mipsel
#define tcg_exec_init tcg_exec_init_mipsel
+#define tcg_expand_vec_op tcg_expand_vec_op_mipsel
#define tcg_find_helper tcg_find_helper_mipsel
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_mipsel
#define tcg_func_start tcg_func_start_mipsel
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mipsel
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mipsel
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mipsel
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_mipsel
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mipsel
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mipsel
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mipsel
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mipsel
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel
#define tcg_gen_goto_tb tcg_gen_goto_tb_mipsel
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_mipsel
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mipsel
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mipsel
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_mipsel
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mipsel
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mipsel
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_mipsel
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mipsel
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mipsel
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mipsel
+#define tcg_gen_gvec_add tcg_gen_gvec_add_mipsel
+#define tcg_gen_gvec_and tcg_gen_gvec_and_mipsel
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_mipsel
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mipsel
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mipsel
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_mipsel
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_mipsel
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_mipsel
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_mipsel
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_mipsel
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_mipsel
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_mipsel
+#define tcg_gen_gvec_not tcg_gen_gvec_not_mipsel
+#define tcg_gen_gvec_or tcg_gen_gvec_or_mipsel
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mipsel
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mipsel
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mipsel
#define tcg_gen_insn_start tcg_gen_insn_start_mipsel
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mipsel
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mipsel
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mipsel
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mipsel
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mipsel
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mipsel
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mipsel
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mipsel
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mipsel
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mipsel
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mipsel
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mipsel
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mipsel
#define tcg_gen_xor_vec tcg_gen_xor_vec_mipsel
diff --git a/qemu/powerpc.h b/qemu/powerpc.h
index 7c00d377..79fe76bc 100644
--- a/qemu/powerpc.h
+++ b/qemu/powerpc.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_powerpc
#define dummy_func dummy_func_powerpc
#define dummy_section dummy_section_powerpc
+#define dup_const_impl dup_const_impl_powerpc
#define end_list end_list_powerpc
#define ensure_writable_pages ensure_writable_pages_powerpc
#define eq128 eq128_powerpc
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_powerpc
#define helper_get_r13_banked helper_get_r13_banked_powerpc
#define helper_get_user_reg helper_get_user_reg_powerpc
+#define helper_gvec_add8 helper_gvec_add8_powerpc
+#define helper_gvec_add16 helper_gvec_add16_powerpc
+#define helper_gvec_add32 helper_gvec_add32_powerpc
+#define helper_gvec_add64 helper_gvec_add64_powerpc
+#define helper_gvec_and helper_gvec_and_powerpc
+#define helper_gvec_andc helper_gvec_andc_powerpc
+#define helper_gvec_dup8 helper_gvec_dup8_powerpc
+#define helper_gvec_dup16 helper_gvec_dup16_powerpc
+#define helper_gvec_dup32 helper_gvec_dup32_powerpc
+#define helper_gvec_dup64 helper_gvec_dup64_powerpc
+#define helper_gvec_mov helper_gvec_mov_powerpc
+#define helper_gvec_neg8 helper_gvec_neg8_powerpc
+#define helper_gvec_neg16 helper_gvec_neg16_powerpc
+#define helper_gvec_neg32 helper_gvec_neg32_powerpc
+#define helper_gvec_neg64 helper_gvec_neg64_powerpc
+#define helper_gvec_not helper_gvec_not_powerpc
+#define helper_gvec_or helper_gvec_or_powerpc
+#define helper_gvec_orc helper_gvec_orc_powerpc
+#define helper_gvec_sub8 helper_gvec_sub8_powerpc
+#define helper_gvec_sub16 helper_gvec_sub16_powerpc
+#define helper_gvec_sub32 helper_gvec_sub32_powerpc
+#define helper_gvec_sub64 helper_gvec_sub64_powerpc
+#define helper_gvec_xor helper_gvec_xor_powerpc
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_powerpc
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_powerpc
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_powerpc
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_powerpc
#define shortShift128Left shortShift128Left_powerpc
#define shortShift192Left shortShift192Left_powerpc
+#define simd_desc simd_desc_powerpc
#define simple_mpu_ap_bits simple_mpu_ap_bits_powerpc
#define size_code_gen_buffer size_code_gen_buffer_powerpc
#define softmmu_lock_user softmmu_lock_user_powerpc
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_powerpc
#define tcg_exec_all tcg_exec_all_powerpc
#define tcg_exec_init tcg_exec_init_powerpc
+#define tcg_expand_vec_op tcg_expand_vec_op_powerpc
#define tcg_find_helper tcg_find_helper_powerpc
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_powerpc
#define tcg_func_start tcg_func_start_powerpc
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_powerpc
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_powerpc
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_powerpc
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_powerpc
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_powerpc
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_powerpc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_powerpc
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_powerpc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc
#define tcg_gen_goto_tb tcg_gen_goto_tb_powerpc
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_powerpc
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_powerpc
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_powerpc
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_powerpc
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_powerpc
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_powerpc
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_powerpc
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_powerpc
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_powerpc
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_powerpc
+#define tcg_gen_gvec_add tcg_gen_gvec_add_powerpc
+#define tcg_gen_gvec_and tcg_gen_gvec_and_powerpc
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_powerpc
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_powerpc
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_powerpc
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_powerpc
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_powerpc
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_powerpc
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_powerpc
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_powerpc
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_powerpc
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_powerpc
+#define tcg_gen_gvec_not tcg_gen_gvec_not_powerpc
+#define tcg_gen_gvec_or tcg_gen_gvec_or_powerpc
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_powerpc
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_powerpc
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_powerpc
#define tcg_gen_insn_start tcg_gen_insn_start_powerpc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_powerpc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_powerpc
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_powerpc
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_powerpc
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_powerpc
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_powerpc
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_powerpc
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_powerpc
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_powerpc
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_powerpc
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_powerpc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_powerpc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_powerpc
#define tcg_gen_xor_vec tcg_gen_xor_vec_powerpc
diff --git a/qemu/sparc.h b/qemu/sparc.h
index 8d6a3a87..70a5b12c 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_sparc
#define dummy_func dummy_func_sparc
#define dummy_section dummy_section_sparc
+#define dup_const_impl dup_const_impl_sparc
#define end_list end_list_sparc
#define ensure_writable_pages ensure_writable_pages_sparc
#define eq128 eq128_sparc
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_sparc
#define helper_get_r13_banked helper_get_r13_banked_sparc
#define helper_get_user_reg helper_get_user_reg_sparc
+#define helper_gvec_add8 helper_gvec_add8_sparc
+#define helper_gvec_add16 helper_gvec_add16_sparc
+#define helper_gvec_add32 helper_gvec_add32_sparc
+#define helper_gvec_add64 helper_gvec_add64_sparc
+#define helper_gvec_and helper_gvec_and_sparc
+#define helper_gvec_andc helper_gvec_andc_sparc
+#define helper_gvec_dup8 helper_gvec_dup8_sparc
+#define helper_gvec_dup16 helper_gvec_dup16_sparc
+#define helper_gvec_dup32 helper_gvec_dup32_sparc
+#define helper_gvec_dup64 helper_gvec_dup64_sparc
+#define helper_gvec_mov helper_gvec_mov_sparc
+#define helper_gvec_neg8 helper_gvec_neg8_sparc
+#define helper_gvec_neg16 helper_gvec_neg16_sparc
+#define helper_gvec_neg32 helper_gvec_neg32_sparc
+#define helper_gvec_neg64 helper_gvec_neg64_sparc
+#define helper_gvec_not helper_gvec_not_sparc
+#define helper_gvec_or helper_gvec_or_sparc
+#define helper_gvec_orc helper_gvec_orc_sparc
+#define helper_gvec_sub8 helper_gvec_sub8_sparc
+#define helper_gvec_sub16 helper_gvec_sub16_sparc
+#define helper_gvec_sub32 helper_gvec_sub32_sparc
+#define helper_gvec_sub64 helper_gvec_sub64_sparc
+#define helper_gvec_xor helper_gvec_xor_sparc
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_sparc
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_sparc
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_sparc
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_sparc
#define shortShift128Left shortShift128Left_sparc
#define shortShift192Left shortShift192Left_sparc
+#define simd_desc simd_desc_sparc
#define simple_mpu_ap_bits simple_mpu_ap_bits_sparc
#define size_code_gen_buffer size_code_gen_buffer_sparc
#define softmmu_lock_user softmmu_lock_user_sparc
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_sparc
#define tcg_exec_all tcg_exec_all_sparc
#define tcg_exec_init tcg_exec_init_sparc
+#define tcg_expand_vec_op tcg_expand_vec_op_sparc
#define tcg_find_helper tcg_find_helper_sparc
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_sparc
#define tcg_func_start tcg_func_start_sparc
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_sparc
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_sparc
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_sparc
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_sparc
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_sparc
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_sparc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_sparc
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_sparc
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_sparc
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_sparc
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc
+#define tcg_gen_gvec_add tcg_gen_gvec_add_sparc
+#define tcg_gen_gvec_and tcg_gen_gvec_and_sparc
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_sparc
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_sparc
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_sparc
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_sparc
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_sparc
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_sparc
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_sparc
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_sparc
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_sparc
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_sparc
+#define tcg_gen_gvec_not tcg_gen_gvec_not_sparc
+#define tcg_gen_gvec_or tcg_gen_gvec_or_sparc
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc
#define tcg_gen_insn_start tcg_gen_insn_start_sparc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_sparc
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_sparc
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_sparc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc
#define tcg_gen_xor_vec tcg_gen_xor_vec_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index 30df2cf1..7b8b71cd 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_sparc64
#define dummy_func dummy_func_sparc64
#define dummy_section dummy_section_sparc64
+#define dup_const_impl dup_const_impl_sparc64
#define end_list end_list_sparc64
#define ensure_writable_pages ensure_writable_pages_sparc64
#define eq128 eq128_sparc64
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_sparc64
#define helper_get_r13_banked helper_get_r13_banked_sparc64
#define helper_get_user_reg helper_get_user_reg_sparc64
+#define helper_gvec_add8 helper_gvec_add8_sparc64
+#define helper_gvec_add16 helper_gvec_add16_sparc64
+#define helper_gvec_add32 helper_gvec_add32_sparc64
+#define helper_gvec_add64 helper_gvec_add64_sparc64
+#define helper_gvec_and helper_gvec_and_sparc64
+#define helper_gvec_andc helper_gvec_andc_sparc64
+#define helper_gvec_dup8 helper_gvec_dup8_sparc64
+#define helper_gvec_dup16 helper_gvec_dup16_sparc64
+#define helper_gvec_dup32 helper_gvec_dup32_sparc64
+#define helper_gvec_dup64 helper_gvec_dup64_sparc64
+#define helper_gvec_mov helper_gvec_mov_sparc64
+#define helper_gvec_neg8 helper_gvec_neg8_sparc64
+#define helper_gvec_neg16 helper_gvec_neg16_sparc64
+#define helper_gvec_neg32 helper_gvec_neg32_sparc64
+#define helper_gvec_neg64 helper_gvec_neg64_sparc64
+#define helper_gvec_not helper_gvec_not_sparc64
+#define helper_gvec_or helper_gvec_or_sparc64
+#define helper_gvec_orc helper_gvec_orc_sparc64
+#define helper_gvec_sub8 helper_gvec_sub8_sparc64
+#define helper_gvec_sub16 helper_gvec_sub16_sparc64
+#define helper_gvec_sub32 helper_gvec_sub32_sparc64
+#define helper_gvec_sub64 helper_gvec_sub64_sparc64
+#define helper_gvec_xor helper_gvec_xor_sparc64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_sparc64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_sparc64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_sparc64
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_sparc64
#define shortShift128Left shortShift128Left_sparc64
#define shortShift192Left shortShift192Left_sparc64
+#define simd_desc simd_desc_sparc64
#define simple_mpu_ap_bits simple_mpu_ap_bits_sparc64
#define size_code_gen_buffer size_code_gen_buffer_sparc64
#define softmmu_lock_user softmmu_lock_user_sparc64
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_sparc64
#define tcg_exec_all tcg_exec_all_sparc64
#define tcg_exec_init tcg_exec_init_sparc64
+#define tcg_expand_vec_op tcg_expand_vec_op_sparc64
#define tcg_find_helper tcg_find_helper_sparc64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_sparc64
#define tcg_func_start tcg_func_start_sparc64
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_sparc64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_sparc64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_sparc64
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_sparc64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_sparc64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_sparc64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc64
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc64
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_sparc64
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc64
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc64
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc64
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_sparc64
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_sparc64
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_sparc64
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc64
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc64
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc64
+#define tcg_gen_gvec_add tcg_gen_gvec_add_sparc64
+#define tcg_gen_gvec_and tcg_gen_gvec_and_sparc64
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_sparc64
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_sparc64
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_sparc64
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_sparc64
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_sparc64
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_sparc64
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_sparc64
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_sparc64
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_sparc64
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_sparc64
+#define tcg_gen_gvec_not tcg_gen_gvec_not_sparc64
+#define tcg_gen_gvec_or tcg_gen_gvec_or_sparc64
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc64
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc64
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc64
#define tcg_gen_insn_start tcg_gen_insn_start_sparc64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc64
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc64
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc64
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc64
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc64
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc64
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc64
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_sparc64
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_sparc64
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_sparc64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc64
#define tcg_gen_xor_vec tcg_gen_xor_vec_sparc64
diff --git a/qemu/tcg-runtime-gvec.c b/qemu/tcg-runtime-gvec.c
new file mode 100644
index 00000000..e0939222
--- /dev/null
+++ b/qemu/tcg-runtime-gvec.c
@@ -0,0 +1,325 @@
+/*
+ * Generic vectorized operation runtime
+ *
+ * Copyright (c) 2018 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "tcg-gvec-desc.h"
+
+
+/* Virtually all hosts support 16-byte vectors. Those that don't can emulate
+ * them via GCC's generic vector extension. This turns out to be simpler and
+ * more reliable than getting the compiler to autovectorize.
+ *
+ * In tcg-op-gvec.c, we asserted that both the size and alignment of the data
+ * are multiples of 16.
+ *
+ * When the compiler does not support all of the operations we require, the
+ * loops are written so that we can always fall back on the base types.
+ */
+#ifdef CONFIG_VECTOR16
+typedef uint8_t vec8 __attribute__((vector_size(16)));
+typedef uint16_t vec16 __attribute__((vector_size(16)));
+typedef uint32_t vec32 __attribute__((vector_size(16)));
+typedef uint64_t vec64 __attribute__((vector_size(16)));
+
+typedef int8_t svec8 __attribute__((vector_size(16)));
+typedef int16_t svec16 __attribute__((vector_size(16)));
+typedef int32_t svec32 __attribute__((vector_size(16)));
+typedef int64_t svec64 __attribute__((vector_size(16)));
+
+#define DUP16(X) { X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X }
+#define DUP8(X) { X, X, X, X, X, X, X, X }
+#define DUP4(X) { X, X, X, X }
+#define DUP2(X) { X, X }
+#else
+typedef uint8_t vec8;
+typedef uint16_t vec16;
+typedef uint32_t vec32;
+typedef uint64_t vec64;
+
+typedef int8_t svec8;
+typedef int16_t svec16;
+typedef int32_t svec32;
+typedef int64_t svec64;
+
+#define DUP16(X) X
+#define DUP8(X) X
+#define DUP4(X) X
+#define DUP2(X) X
+#endif /* CONFIG_VECTOR16 */
+
+static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
+{
+ intptr_t maxsz = simd_maxsz(desc);
+ intptr_t i;
+
+ if (unlikely(maxsz > oprsz)) {
+ for (i = oprsz; i < maxsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = 0;
+ }
+ }
+}
+
+void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = -*(vec8 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg16)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = -*(vec16 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg32)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = -*(vec32 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = -*(vec64 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mov)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+
+ memcpy(d, a, oprsz);
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup64)(void *d, uint32_t desc, uint64_t c)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ if (c == 0) {
+ oprsz = 0;
+ } else {
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = c;
+ }
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup32)(void *d, uint32_t desc, uint32_t c)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ if (c == 0) {
+ oprsz = 0;
+ } else {
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = c;
+ }
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup16)(void *d, uint32_t desc, uint32_t c)
+{
+ HELPER(gvec_dup32)(d, desc, 0x00010001 * (c & 0xffff));
+}
+
+void HELPER(gvec_dup8)(void *d, uint32_t desc, uint32_t c)
+{
+ HELPER(gvec_dup32)(d, desc, 0x01010101 * (c & 0xff));
+}
+
+void HELPER(gvec_not)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = ~*(vec64 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_and)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_or)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_xor)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_andc)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
diff --git a/qemu/tcg/tcg-gvec-desc.h b/qemu/tcg/tcg-gvec-desc.h
new file mode 100644
index 00000000..3b4c2d9c
--- /dev/null
+++ b/qemu/tcg/tcg-gvec-desc.h
@@ -0,0 +1,49 @@
+/*
+ * Generic vector operation descriptor
+ *
+ * Copyright (c) 2018 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
+#define SIMD_OPRSZ_SHIFT 0
+#define SIMD_OPRSZ_BITS 5
+
+#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
+#define SIMD_MAXSZ_BITS 5
+
+#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
+
+/* Create a descriptor from components. */
+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
+
+/* Extract the operation size from a descriptor. */
+static inline intptr_t simd_oprsz(uint32_t desc)
+{
+ return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
+}
+
+/* Extract the max vector size from a descriptor. */
+static inline intptr_t simd_maxsz(uint32_t desc)
+{
+ return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
+}
+
+/* Extract the operation-specific data from a descriptor. */
+static inline int32_t simd_data(uint32_t desc)
+{
+ return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
+}
diff --git a/qemu/tcg/tcg-op-gvec.c b/qemu/tcg/tcg-op-gvec.c
new file mode 100644
index 00000000..9317f509
--- /dev/null
+++ b/qemu/tcg/tcg-op-gvec.c
@@ -0,0 +1,1309 @@
+/*
+ * Generic vector operation expansion
+ *
+ * Copyright (c) 2018 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "tcg.h"
+#include "tcg-op.h"
+#include "tcg-op-gvec.h"
+#include "tcg-gvec-desc.h"
+
+#define MAX_UNROLL 4
+
+/* Verify vector size and alignment rules. OFS should be the OR of all
+ of the operand offsets so that we can check them all at once. */
+static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
+{
+ uint32_t opr_align = oprsz >= 16 ? 15 : 7;
+ uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
+ tcg_debug_assert(oprsz > 0);
+ tcg_debug_assert(oprsz <= maxsz);
+ tcg_debug_assert((oprsz & opr_align) == 0);
+ tcg_debug_assert((maxsz & max_align) == 0);
+ tcg_debug_assert((ofs & max_align) == 0);
+}
+
+/* Verify vector overlap rules for two operands. */
+static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s)
+{
+ tcg_debug_assert(d == a || d + s <= a || a + s <= d);
+}
+
+/* Verify vector overlap rules for three operands. */
+static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s)
+{
+ check_overlap_2(d, a, s);
+ check_overlap_2(d, b, s);
+ check_overlap_2(a, b, s);
+}
+
+/* Verify vector overlap rules for four operands. */
+static void check_overlap_4(uint32_t d, uint32_t a, uint32_t b,
+ uint32_t c, uint32_t s)
+{
+ check_overlap_2(d, a, s);
+ check_overlap_2(d, b, s);
+ check_overlap_2(d, c, s);
+ check_overlap_2(a, b, s);
+ check_overlap_2(a, c, s);
+ check_overlap_2(b, c, s);
+}
+
+/* Create a descriptor from components. */
+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
+{
+ uint32_t desc = 0;
+
+ assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
+ assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
+ assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+
+ oprsz = (oprsz / 8) - 1;
+ maxsz = (maxsz / 8) - 1;
+ desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
+ desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
+ desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
+
+ return desc;
+}
+
+/* Generate a call to a gvec-style helper with two vector operands. */
+void tcg_gen_gvec_2_ool(TCGContext *s, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2 *fn)
+{
+ TCGv_ptr a0, a1;
+ TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr(s);
+ a1 = tcg_temp_new_ptr(s);
+
+ tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
+ tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+
+ fn(s, a0, a1, desc);
+
+ tcg_temp_free_ptr(s, a0);
+ tcg_temp_free_ptr(s, a1);
+ tcg_temp_free_i32(s, desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands. */
+void tcg_gen_gvec_3_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_3 *fn)
+{
+ TCGv_ptr a0, a1, a2;
+ TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr(s);
+ a1 = tcg_temp_new_ptr(s);
+ a2 = tcg_temp_new_ptr(s);
+
+ tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
+ tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+ tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
+
+ fn(s, a0, a1, a2, desc);
+
+ tcg_temp_free_ptr(s, a0);
+ tcg_temp_free_ptr(s, a1);
+ tcg_temp_free_ptr(s, a2);
+ tcg_temp_free_i32(s, desc);
+}
+
+/* Generate a call to a gvec-style helper with four vector operands. */
+void tcg_gen_gvec_4_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_4 *fn)
+{
+ TCGv_ptr a0, a1, a2, a3;
+ TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr(s);
+ a1 = tcg_temp_new_ptr(s);
+ a2 = tcg_temp_new_ptr(s);
+ a3 = tcg_temp_new_ptr(s);
+
+ tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
+ tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+ tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
+ tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
+
+ fn(s, a0, a1, a2, a3, desc);
+
+ tcg_temp_free_ptr(s, a0);
+ tcg_temp_free_ptr(s, a1);
+ tcg_temp_free_ptr(s, a2);
+ tcg_temp_free_ptr(s, a3);
+ tcg_temp_free_i32(s, desc);
+}
+
+/* Generate a call to a gvec-style helper with five vector operands. */
+void tcg_gen_gvec_5_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t xofs, uint32_t oprsz,
+ uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn)
+{
+ TCGv_ptr a0, a1, a2, a3, a4;
+ TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr(s);
+ a1 = tcg_temp_new_ptr(s);
+ a2 = tcg_temp_new_ptr(s);
+ a3 = tcg_temp_new_ptr(s);
+ a4 = tcg_temp_new_ptr(s);
+
+ tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
+ tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+ tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
+ tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
+ tcg_gen_addi_ptr(s, a4, s->cpu_env, xofs);
+
+ fn(s, a0, a1, a2, a3, a4, desc);
+
+ tcg_temp_free_ptr(s, a0);
+ tcg_temp_free_ptr(s, a1);
+ tcg_temp_free_ptr(s, a2);
+ tcg_temp_free_ptr(s, a3);
+ tcg_temp_free_ptr(s, a4);
+ tcg_temp_free_i32(s, desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_2_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_2_ptr *fn)
+{
+ TCGv_ptr a0, a1;
+ TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr(s);
+ a1 = tcg_temp_new_ptr(s);
+
+ tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
+ tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+
+ fn(s, a0, a1, ptr, desc);
+
+ tcg_temp_free_ptr(s, a0);
+ tcg_temp_free_ptr(s, a1);
+ tcg_temp_free_i32(s, desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_3_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_3_ptr *fn)
+{
+ TCGv_ptr a0, a1, a2;
+ TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr(s);
+ a1 = tcg_temp_new_ptr(s);
+ a2 = tcg_temp_new_ptr(s);
+
+ tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
+ tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+ tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
+
+ fn(s, a0, a1, a2, ptr, desc);
+
+ tcg_temp_free_ptr(s, a0);
+ tcg_temp_free_ptr(s, a1);
+ tcg_temp_free_ptr(s, a2);
+ tcg_temp_free_i32(s, desc);
+}
+
+/* Generate a call to a gvec-style helper with four vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
+ uint32_t maxsz, int32_t data,
+ gen_helper_gvec_4_ptr *fn)
+{
+ TCGv_ptr a0, a1, a2, a3;
+ TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr(s);
+ a1 = tcg_temp_new_ptr(s);
+ a2 = tcg_temp_new_ptr(s);
+ a3 = tcg_temp_new_ptr(s);
+
+ tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
+ tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+ tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
+ tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
+
+ fn(s, a0, a1, a2, a3, ptr, desc);
+
+ tcg_temp_free_ptr(s, a0);
+ tcg_temp_free_ptr(s, a1);
+ tcg_temp_free_ptr(s, a2);
+ tcg_temp_free_ptr(s, a3);
+ tcg_temp_free_i32(s, desc);
+}
+
+/* Return true if we want to implement something of OPRSZ bytes
+ in units of LNSZ. This limits the expansion of inline code. */
+static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
+{
+ uint32_t lnct = oprsz / lnsz;
+ return lnct >= 1 && lnct <= MAX_UNROLL;
+}
+
+static void expand_clr(TCGContext *s, uint32_t dofs, uint32_t maxsz);
+
+/* Duplicate C as per VECE. */
+uint64_t (dup_const_impl)(unsigned vece, uint64_t c)
+{
+ switch (vece) {
+ case MO_8:
+ return 0x0101010101010101ull * (uint8_t)c;
+ case MO_16:
+ return 0x0001000100010001ull * (uint16_t)c;
+ case MO_32:
+ return 0x0000000100000001ull * (uint32_t)c;
+ case MO_64:
+ return c;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+/* Duplicate IN into OUT as per VECE. */
+static void gen_dup_i32(TCGContext *s, unsigned vece, TCGv_i32 out, TCGv_i32 in)
+{
+ switch (vece) {
+ case MO_8:
+ tcg_gen_ext8u_i32(s, out, in);
+ tcg_gen_muli_i32(s, out, out, 0x01010101);
+ break;
+ case MO_16:
+ tcg_gen_deposit_i32(s, out, in, in, 16, 16);
+ break;
+ case MO_32:
+ tcg_gen_mov_i32(s, out, in);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void gen_dup_i64(TCGContext *s, unsigned vece, TCGv_i64 out, TCGv_i64 in)
+{
+ switch (vece) {
+ case MO_8:
+ tcg_gen_ext8u_i64(s, out, in);
+ tcg_gen_muli_i64(s, out, out, 0x0101010101010101ull);
+ break;
+ case MO_16:
+ tcg_gen_ext16u_i64(s, out, in);
+ tcg_gen_muli_i64(s, out, out, 0x0001000100010001ull);
+ break;
+ case MO_32:
+ tcg_gen_deposit_i64(s, out, in, in, 32, 32);
+ break;
+ case MO_64:
+ tcg_gen_mov_i64(s, out, in);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+/* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C.
+ * Only one of IN_32 or IN_64 may be set;
+ * IN_C is used if IN_32 and IN_64 are unset.
+ */
+static void do_dup(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i32 in_32, TCGv_i64 in_64,
+ uint64_t in_c)
+{
+ TCGType type;
+ TCGv_i64 t_64;
+ TCGv_i32 t_32, t_desc;
+ TCGv_ptr t_ptr;
+ uint32_t i;
+
+ assert(vece <= (in_32 ? MO_32 : MO_64));
+ assert(in_32 == NULL || in_64 == NULL);
+
+ /* If we're storing 0, expand oprsz to maxsz. */
+ if (in_32 == NULL && in_64 == NULL) {
+ in_c = dup_const(vece, in_c);
+ if (in_c == 0) {
+ oprsz = maxsz;
+ }
+ }
+
+ type = 0;
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ type = TCG_TYPE_V256;
+ } else if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ type = TCG_TYPE_V128;
+ } else if (TCG_TARGET_HAS_v64 && check_size_impl(oprsz, 8)
+ /* Prefer integer when 64-bit host and no variable dup. */
+ && !(TCG_TARGET_REG_BITS == 64 && in_32 == NULL
+ && (in_64 == NULL || vece == MO_64))) {
+ type = TCG_TYPE_V64;
+ }
+
+ /* Implement inline with a vector type, if possible. */
+ if (type != 0) {
+ TCGv_vec t_vec = tcg_temp_new_vec(s, type);
+
+ if (in_32) {
+ tcg_gen_dup_i32_vec(s, vece, t_vec, in_32);
+ } else if (in_64) {
+ tcg_gen_dup_i64_vec(s, vece, t_vec, in_64);
+ } else {
+ switch (vece) {
+ case MO_8:
+ tcg_gen_dup8i_vec(s, t_vec, in_c);
+ break;
+ case MO_16:
+ tcg_gen_dup16i_vec(s, t_vec, in_c);
+ break;
+ case MO_32:
+ tcg_gen_dup32i_vec(s, t_vec, in_c);
+ break;
+ default:
+ tcg_gen_dup64i_vec(s, t_vec, in_c);
+ break;
+ }
+ }
+
+ i = 0;
+ if (TCG_TARGET_HAS_v256) {
+ for (; i + 32 <= oprsz; i += 32) {
+ tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V256);
+ }
+ }
+ if (TCG_TARGET_HAS_v128) {
+ for (; i + 16 <= oprsz; i += 16) {
+ tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V128);
+ }
+ }
+ if (TCG_TARGET_HAS_v64) {
+ for (; i < oprsz; i += 8) {
+ tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V64);
+ }
+ }
+ tcg_temp_free_vec(s, t_vec);
+ goto done;
+ }
+
+ /* Otherwise, inline with an integer type, unless "large". */
+ if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) {
+ t_64 = NULL;
+ t_32 = NULL;
+
+ if (in_32) {
+ /* We are given a 32-bit variable input. For a 64-bit host,
+ use a 64-bit operation unless the 32-bit operation would
+ be simple enough. */
+ if (TCG_TARGET_REG_BITS == 64
+ && (vece != MO_32 || !check_size_impl(oprsz, 4))) {
+ t_64 = tcg_temp_new_i64(s);
+ tcg_gen_extu_i32_i64(s, t_64, in_32);
+ gen_dup_i64(s, vece, t_64, t_64);
+ } else {
+ t_32 = tcg_temp_new_i32(s);
+ gen_dup_i32(s, vece, t_32, in_32);
+ }
+ } else if (in_64) {
+ /* We are given a 64-bit variable input. */
+ t_64 = tcg_temp_new_i64(s);
+ gen_dup_i64(s, vece, t_64, in_64);
+ } else {
+ /* We are given a constant input. */
+ /* For 64-bit hosts, use 64-bit constants for "simple" constants
+ or when we'd need too many 32-bit stores, or when a 64-bit
+ constant is really required. */
+ if (vece == MO_64
+ || (TCG_TARGET_REG_BITS == 64
+ && (in_c == 0 || in_c == -1
+ || !check_size_impl(oprsz, 4)))) {
+ t_64 = tcg_const_i64(s, in_c);
+ } else {
+ t_32 = tcg_const_i32(s, in_c);
+ }
+ }
+
+ /* Implement inline if we picked an implementation size above. */
+ if (t_32) {
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_st_i32(s, t_32, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(s, t_32);
+ goto done;
+ }
+ if (t_64) {
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_st_i64(s, t_64, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(s, t_64);
+ goto done;
+ }
+ }
+
+ /* Otherwise implement out of line. */
+ t_ptr = tcg_temp_new_ptr(s);
+ tcg_gen_addi_ptr(s, t_ptr, s->cpu_env, dofs);
+ t_desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, 0));
+
+ if (vece == MO_64) {
+ if (in_64) {
+ gen_helper_gvec_dup64(s, t_ptr, t_desc, in_64);
+ } else {
+ t_64 = tcg_const_i64(s, in_c);
+ gen_helper_gvec_dup64(s, t_ptr, t_desc, t_64);
+ tcg_temp_free_i64(s, t_64);
+ }
+ } else {
+ typedef void dup_fn(TCGContext *, TCGv_ptr, TCGv_i32, TCGv_i32);
+ static dup_fn * const fns[3] = {
+ gen_helper_gvec_dup8,
+ gen_helper_gvec_dup16,
+ gen_helper_gvec_dup32
+ };
+
+ if (in_32) {
+ fns[vece](s, t_ptr, t_desc, in_32);
+ } else {
+ t_32 = tcg_temp_new_i32(s);
+ if (in_64) {
+ tcg_gen_extrl_i64_i32(s, t_32, in_64);
+ } else if (vece == MO_8) {
+ tcg_gen_movi_i32(s, t_32, in_c & 0xff);
+ } else if (vece == MO_16) {
+ tcg_gen_movi_i32(s, t_32, in_c & 0xffff);
+ } else {
+ tcg_gen_movi_i32(s, t_32, in_c);
+ }
+ fns[vece](s, t_ptr, t_desc, t_32);
+ tcg_temp_free_i32(s, t_32);
+ }
+ }
+
+ tcg_temp_free_ptr(s, t_ptr);
+ tcg_temp_free_i32(s, t_desc);
+ return;
+
+ done:
+ if (oprsz < maxsz) {
+ expand_clr(s, dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/* Likewise, but with zero. */
+static void expand_clr(TCGContext *s, uint32_t dofs, uint32_t maxsz)
+{
+ do_dup(s, MO_8, dofs, maxsz, maxsz, NULL, NULL, 0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
+static void expand_2_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ void (*fni)(TCGContext *, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32(s);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
+ fni(s, t0, t0);
+ tcg_gen_st_i32(s, t0, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(s, t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
+static void expand_3_i32(TCGContext *s, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, bool load_dest,
+ void (*fni)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32(s);
+ TCGv_i32 t1 = tcg_temp_new_i32(s);
+ TCGv_i32 t2 = tcg_temp_new_i32(s);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
+ tcg_gen_ld_i32(s, t1, s->cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i32(s, t2, s->cpu_env, dofs + i);
+ }
+ fni(s, t2, t0, t1);
+ tcg_gen_st_i32(s, t2, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(s, t2);
+ tcg_temp_free_i32(s, t1);
+ tcg_temp_free_i32(s, t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
+static void expand_4_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz,
+ void (*fni)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32(s);
+ TCGv_i32 t1 = tcg_temp_new_i32(s);
+ TCGv_i32 t2 = tcg_temp_new_i32(s);
+ TCGv_i32 t3 = tcg_temp_new_i32(s);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(s, t1, s->cpu_env, aofs + i);
+ tcg_gen_ld_i32(s, t2, s->cpu_env, bofs + i);
+ tcg_gen_ld_i32(s, t3, s->cpu_env, cofs + i);
+ fni(s, t0, t1, t2, t3);
+ tcg_gen_st_i32(s, t0, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(s, t3);
+ tcg_temp_free_i32(s, t2);
+ tcg_temp_free_i32(s, t1);
+ tcg_temp_free_i32(s, t0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
+static void expand_2_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ void (*fni)(TCGContext *, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64(s);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
+ fni(s, t0, t0);
+ tcg_gen_st_i64(s, t0, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(s, t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
+static void expand_3_i64(TCGContext *s, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, bool load_dest,
+ void (*fni)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64(s);
+ TCGv_i64 t1 = tcg_temp_new_i64(s);
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
+ tcg_gen_ld_i64(s, t1, s->cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i64(s, t2, s->cpu_env, dofs + i);
+ }
+ fni(s, t2, t0, t1);
+ tcg_gen_st_i64(s, t2, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(s, t2);
+ tcg_temp_free_i64(s, t1);
+ tcg_temp_free_i64(s, t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
+static void expand_4_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz,
+ void (*fni)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64(s);
+ TCGv_i64 t1 = tcg_temp_new_i64(s);
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+ TCGv_i64 t3 = tcg_temp_new_i64(s);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(s, t1, s->cpu_env, aofs + i);
+ tcg_gen_ld_i64(s, t2, s->cpu_env, bofs + i);
+ tcg_gen_ld_i64(s, t3, s->cpu_env, cofs + i);
+ fni(s, t0, t1, t2, t3);
+ tcg_gen_st_i64(s, t0, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(s, t3);
+ tcg_temp_free_i64(s, t2);
+ tcg_temp_free_i64(s, t1);
+ tcg_temp_free_i64(s, t0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
+static void expand_2_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t tysz, TCGType type,
+ void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(s, type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
+ fni(s, vece, t0, t0);
+ tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(s, t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
+static void expand_3_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz,
+ uint32_t tysz, TCGType type, bool load_dest,
+ void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(s, type);
+ TCGv_vec t1 = tcg_temp_new_vec(s, type);
+ TCGv_vec t2 = tcg_temp_new_vec(s, type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
+ tcg_gen_ld_vec(s, t1, s->cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_vec(s, t2, s->cpu_env, dofs + i);
+ }
+ fni(s, vece, t2, t0, t1);
+ tcg_gen_st_vec(s, t2, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(s, t2);
+ tcg_temp_free_vec(s, t1);
+ tcg_temp_free_vec(s, t0);
+}
+
+/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
+static void expand_4_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t cofs, uint32_t oprsz,
+ uint32_t tysz, TCGType type,
+ void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec,
+ TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(s, type);
+ TCGv_vec t1 = tcg_temp_new_vec(s, type);
+ TCGv_vec t2 = tcg_temp_new_vec(s, type);
+ TCGv_vec t3 = tcg_temp_new_vec(s, type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(s, t1, s->cpu_env, aofs + i);
+ tcg_gen_ld_vec(s, t2, s->cpu_env, bofs + i);
+ tcg_gen_ld_vec(s, t3, s->cpu_env, cofs + i);
+ fni(s, vece, t0, t1, t2, t3);
+ tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(s, t3);
+ tcg_temp_free_vec(s, t2);
+ tcg_temp_free_vec(s, t1);
+ tcg_temp_free_vec(s, t0);
+}
+
+/* Expand a vector two-operand operation. */
+void tcg_gen_gvec_2(TCGContext *s, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, maxsz);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+ /* ??? For maxsz > oprsz, the host may be able to use an opr-sized
+ operation, zeroing the balance of the register. We can then
+ use a max-sized store to implement the clearing without an extra
+ store operation. This is true for aarch64 and x86_64 hosts. */
+
+ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_2_vec(s, g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv);
+ if (some == oprsz) {
+ goto done;
+ }
+ dofs += some;
+ aofs += some;
+ oprsz -= some;
+ maxsz -= some;
+ }
+
+ if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ expand_2_vec(s, g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && g->fniv && check_size_impl(oprsz, 8)
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_2_vec(s, g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_2_i64(s, dofs, aofs, oprsz, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_2_i32(s, dofs, aofs, oprsz, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_2_ool(s, dofs, aofs, oprsz, maxsz, g->data, g->fno);
+ return;
+ }
+
+ done:
+ if (oprsz < maxsz) {
+ expand_clr(s, dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/* Expand a vector three-operand operation. */
+void tcg_gen_gvec_3(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, maxsz);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+
+ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_3_vec(s, g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
+ g->load_dest, g->fniv);
+ if (some == oprsz) {
+ goto done;
+ }
+ dofs += some;
+ aofs += some;
+ bofs += some;
+ oprsz -= some;
+ maxsz -= some;
+ }
+
+ if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ expand_3_vec(s, g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
+ g->load_dest, g->fniv);
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && g->fniv && check_size_impl(oprsz, 8)
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_3_vec(s, g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
+ g->load_dest, g->fniv);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_3_i64(s, dofs, aofs, bofs, oprsz, g->load_dest, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_3_i32(s, dofs, aofs, bofs, oprsz, g->load_dest, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_3_ool(s, dofs, aofs, bofs, oprsz, maxsz, g->data, g->fno);
+ }
+
+ done:
+ if (oprsz < maxsz) {
+ expand_clr(s, dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/* Expand a vector four-operand operation. */
+void tcg_gen_gvec_4(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
+ check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+
+ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_4_vec(s, g->vece, dofs, aofs, bofs, cofs, some,
+ 32, TCG_TYPE_V256, g->fniv);
+ if (some == oprsz) {
+ goto done;
+ }
+ dofs += some;
+ aofs += some;
+ bofs += some;
+ cofs += some;
+ oprsz -= some;
+ maxsz -= some;
+ }
+
+ if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ expand_4_vec(s, g->vece, dofs, aofs, bofs, cofs, oprsz,
+ 16, TCG_TYPE_V128, g->fniv);
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && g->fniv && check_size_impl(oprsz, 8)
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_4_vec(s, g->vece, dofs, aofs, bofs, cofs, oprsz,
+ 8, TCG_TYPE_V64, g->fniv);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_4_i64(s, dofs, aofs, bofs, cofs, oprsz, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_4_i32(s, dofs, aofs, bofs, cofs, oprsz, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_4_ool(s, dofs, aofs, bofs, cofs,
+ oprsz, maxsz, g->data, g->fno);
+ return;
+ }
+
+ done:
+ if (oprsz < maxsz) {
+ expand_clr(s, dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/*
+ * Expand specific vector operations.
+ */
+
+static void vec_mov2(TCGContext *s, unsigned vece, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_mov_vec(s, a, b);
+}
+
+void tcg_gen_gvec_mov(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2 g = {
+ .fni8 = tcg_gen_mov_i64,
+ .fniv = vec_mov2,
+ .fno = gen_helper_gvec_mov,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ if (dofs != aofs) {
+ tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g);
+ } else {
+ check_size_align(oprsz, maxsz, dofs);
+ if (oprsz < maxsz) {
+ expand_clr(s, dofs + oprsz, maxsz - oprsz);
+ }
+ }
+}
+
+void tcg_gen_gvec_dup_i32(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i32 in)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ tcg_debug_assert(vece <= MO_32);
+ do_dup(s, vece, dofs, oprsz, maxsz, in, NULL, 0);
+}
+
+void tcg_gen_gvec_dup_i64(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i64 in)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ tcg_debug_assert(vece <= MO_64);
+ do_dup(s, vece, dofs, oprsz, maxsz, NULL, in, 0);
+}
+
+void tcg_gen_gvec_dup_mem(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ if (vece <= MO_32) {
+ TCGv_i32 in = tcg_temp_new_i32(s);
+ switch (vece) {
+ case MO_8:
+ tcg_gen_ld8u_i32(s, in, s->cpu_env, aofs);
+ break;
+ case MO_16:
+ tcg_gen_ld16u_i32(s, in, s->cpu_env, aofs);
+ break;
+ case MO_32:
+ tcg_gen_ld_i32(s, in, s->cpu_env, aofs);
+ break;
+ }
+ tcg_gen_gvec_dup_i32(s, vece, dofs, oprsz, maxsz, in);
+ tcg_temp_free_i32(s, in);
+ } else if (vece == MO_64) {
+ TCGv_i64 in = tcg_temp_new_i64(s);
+ tcg_gen_ld_i64(s, in, s->cpu_env, aofs);
+ tcg_gen_gvec_dup_i64(s, MO_64, dofs, oprsz, maxsz, in);
+ tcg_temp_free_i64(s, in);
+ } else {
+ /* 128-bit duplicate. */
+ /* ??? Dup to 256-bit vector. */
+ int i;
+
+ tcg_debug_assert(vece == 4);
+ tcg_debug_assert(oprsz >= 16);
+ if (TCG_TARGET_HAS_v128) {
+ TCGv_vec in = tcg_temp_new_vec(s, TCG_TYPE_V128);
+
+ tcg_gen_ld_vec(s, in, s->cpu_env, aofs);
+ for (i = 0; i < oprsz; i += 16) {
+ tcg_gen_st_vec(s, in, s->cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(s, in);
+ } else {
+ TCGv_i64 in0 = tcg_temp_new_i64(s);
+ TCGv_i64 in1 = tcg_temp_new_i64(s);
+
+ tcg_gen_ld_i64(s, in0, s->cpu_env, aofs);
+ tcg_gen_ld_i64(s, in1, s->cpu_env, aofs + 8);
+ for (i = 0; i < oprsz; i += 16) {
+ tcg_gen_st_i64(s, in0, s->cpu_env, dofs + i);
+ tcg_gen_st_i64(s, in1, s->cpu_env, dofs + i + 8);
+ }
+ tcg_temp_free_i64(s, in0);
+ tcg_temp_free_i64(s, in1);
+ }
+ }
+}
+
+void tcg_gen_gvec_dup64i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint64_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(s, MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_dup32i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint32_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(s, MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_dup16i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint16_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(s, MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_dup8i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint8_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(s, MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_not(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2 g = {
+ .fni8 = tcg_gen_not_i64,
+ .fniv = tcg_gen_not_vec,
+ .fno = gen_helper_gvec_not,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g);
+}
+
+/* Perform a vector addition using normal addition and a mask. The mask
+ should be the sign bit of each lane. This 6-operation form is more
+ efficient than separate additions when there are 4 or more lanes in
+ the 64-bit operation. */
+static void gen_addv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64(s);
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+ TCGv_i64 t3 = tcg_temp_new_i64(s);
+
+ tcg_gen_andc_i64(s, t1, a, m);
+ tcg_gen_andc_i64(s, t2, b, m);
+ tcg_gen_xor_i64(s, t3, a, b);
+ tcg_gen_add_i64(s, d, t1, t2);
+ tcg_gen_and_i64(s, t3, t3, m);
+ tcg_gen_xor_i64(s, d, d, t3);
+
+ tcg_temp_free_i64(s, t1);
+ tcg_temp_free_i64(s, t2);
+ tcg_temp_free_i64(s, t3);
+}
+
+void tcg_gen_vec_add8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(s, dup_const(MO_8, 0x80));
+ gen_addv_mask(s, d, a, b, m);
+ tcg_temp_free_i64(s, m);
+}
+
+void tcg_gen_vec_add16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(s, dup_const(MO_16, 0x8000));
+ gen_addv_mask(s, d, a, b, m);
+ tcg_temp_free_i64(s, m);
+}
+
+void tcg_gen_vec_add32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64(s);
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+
+ tcg_gen_andi_i64(s, t1, a, ~0xffffffffull);
+ tcg_gen_add_i64(s, t2, a, b);
+ tcg_gen_add_i64(s, t1, t1, b);
+ tcg_gen_deposit_i64(s, d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(s, t1);
+ tcg_temp_free_i64(s, t2);
+}
+
+void tcg_gen_gvec_add(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = tcg_gen_vec_add8_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add8,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_add16_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add16,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_add_i32,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add32,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_add_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add64,
+ .opc = INDEX_op_add_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+/* Perform a vector subtraction using normal subtraction and a mask.
+ Compare gen_addv_mask above. */
+static void gen_subv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64(s);
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+ TCGv_i64 t3 = tcg_temp_new_i64(s);
+
+ tcg_gen_or_i64(s, t1, a, m);
+ tcg_gen_andc_i64(s, t2, b, m);
+ tcg_gen_eqv_i64(s, t3, a, b);
+ tcg_gen_sub_i64(s, d, t1, t2);
+ tcg_gen_and_i64(s, t3, t3, m);
+ tcg_gen_xor_i64(s, d, d, t3);
+
+ tcg_temp_free_i64(s, t1);
+ tcg_temp_free_i64(s, t2);
+ tcg_temp_free_i64(s, t3);
+}
+
+void tcg_gen_vec_sub8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(s, dup_const(MO_8, 0x80));
+ gen_subv_mask(s, d, a, b, m);
+ tcg_temp_free_i64(s, m);
+}
+
+void tcg_gen_vec_sub16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(s, dup_const(MO_16, 0x8000));
+ gen_subv_mask(s, d, a, b, m);
+ tcg_temp_free_i64(s, m);
+}
+
+void tcg_gen_vec_sub32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64(s);
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+
+ tcg_gen_andi_i64(s, t1, b, ~0xffffffffull);
+ tcg_gen_sub_i64(s, t2, a, b);
+ tcg_gen_sub_i64(s, t1, a, t1);
+ tcg_gen_deposit_i64(s, d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(s, t1);
+ tcg_temp_free_i64(s, t2);
+}
+
+void tcg_gen_gvec_sub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = tcg_gen_vec_sub8_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub8,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_sub16_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub16,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_sub_i32,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub32,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_sub_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub64,
+ .opc = INDEX_op_sub_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+/* Perform a vector negation using normal negation and a mask.
+ Compare gen_subv_mask above. */
+static void gen_negv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+ TCGv_i64 t3 = tcg_temp_new_i64(s);
+
+ tcg_gen_andc_i64(s, t3, m, b);
+ tcg_gen_andc_i64(s, t2, b, m);
+ tcg_gen_sub_i64(s, d, m, t2);
+ tcg_gen_xor_i64(s, d, d, t3);
+
+ tcg_temp_free_i64(s, t2);
+ tcg_temp_free_i64(s, t3);
+}
+
+void tcg_gen_vec_neg8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(s, dup_const(MO_8, 0x80));
+ gen_negv_mask(s, d, b, m);
+ tcg_temp_free_i64(s, m);
+}
+
+void tcg_gen_vec_neg16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(s, dup_const(MO_16, 0x8000));
+ gen_negv_mask(s, d, b, m);
+ tcg_temp_free_i64(s, m);
+}
+
+void tcg_gen_vec_neg32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64(s);
+ TCGv_i64 t2 = tcg_temp_new_i64(s);
+
+ tcg_gen_andi_i64(s, t1, b, ~0xffffffffull);
+ tcg_gen_neg_i64(s, t2, b);
+ tcg_gen_neg_i64(s, t1, t1);
+ tcg_gen_deposit_i64(s, d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(s, t1);
+ tcg_temp_free_i64(s, t2);
+}
+
+void tcg_gen_gvec_neg(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2 g[4] = {
+ { .fni8 = tcg_gen_vec_neg8_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg8,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_neg16_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg16,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_neg_i32,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg32,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_neg_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg64,
+ .opc = INDEX_op_neg_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g[vece]);
+}
+
+void tcg_gen_gvec_and(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_and_i64,
+ .fniv = tcg_gen_and_vec,
+ .fno = gen_helper_gvec_and,
+ .opc = INDEX_op_and_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_or(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_or_i64,
+ .fniv = tcg_gen_or_vec,
+ .fno = gen_helper_gvec_or,
+ .opc = INDEX_op_or_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_xor(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_xor_i64,
+ .fniv = tcg_gen_xor_vec,
+ .fno = gen_helper_gvec_xor,
+ .opc = INDEX_op_xor_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_andc(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_andc_i64,
+ .fniv = tcg_gen_andc_vec,
+ .fno = gen_helper_gvec_andc,
+ .opc = INDEX_op_andc_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_orc(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_orc_i64,
+ .fniv = tcg_gen_orc_vec,
+ .fno = gen_helper_gvec_orc,
+ .opc = INDEX_op_orc_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
+}
diff --git a/qemu/tcg/tcg-op-gvec.h b/qemu/tcg/tcg-op-gvec.h
new file mode 100644
index 00000000..b50a05ce
--- /dev/null
+++ b/qemu/tcg/tcg-op-gvec.h
@@ -0,0 +1,198 @@
+/*
+ * Generic vector operation expansion
+ *
+ * Copyright (c) 2018 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+/*
+ * "Generic" vectors. All operands are given as offsets from ENV,
+ * and therefore cannot also be allocated via tcg_global_mem_new_*.
+ * OPRSZ is the byte size of the vector upon which the operation is performed.
+ * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
+ *
+ * All sizes must be 8 or any multiple of 16.
+ * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
+ * Operands may completely, but not partially, overlap.
+ */
+
+/* Expand a call to a gvec-style helper, with pointers to two vector
+ operands, and a descriptor (see tcg-gvec-desc.h). */
+typedef void gen_helper_gvec_2(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ool(TCGContext *, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2 *fn);
+
+/* Similarly, passing an extra pointer (e.g. env or float_status). */
+typedef void gen_helper_gvec_2_ptr(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ptr(TCGContext *, uint32_t dofs, uint32_t aofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_2_ptr *fn);
+
+/* Similarly, with three vector operands. */
+typedef void gen_helper_gvec_3(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ool(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_3 *fn);
+
+/* Similarly, with four vector operands. */
+typedef void gen_helper_gvec_4(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_4_ool(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_4 *fn);
+
+/* Similarly, with five vector operands. */
+typedef void gen_helper_gvec_5(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_5_ool(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t xofs, uint32_t oprsz,
+ uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn);
+
+typedef void gen_helper_gvec_3_ptr(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ptr(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_3_ptr *fn);
+
+typedef void gen_helper_gvec_4_ptr(TCGContext *s, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
+ uint32_t maxsz, int32_t data,
+ gen_helper_gvec_4_ptr *fn);
+
+/* Expand a gvec operation. Either inline or out-of-line depending on
+ the actual vector size and the operations supported by the host. */
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_2 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ int32_t data;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+} GVecGen2;
+
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGContext *s, TCGv_i64, TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGContext *s, TCGv_i32, TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_3 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ int32_t data;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load dest as a 3rd source operand. */
+ bool load_dest;
+} GVecGen3;
+
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGContext *s, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGContext *s, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_4 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ int32_t data;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+} GVecGen4;
+
+void tcg_gen_gvec_2(TCGContext *, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
+void tcg_gen_gvec_3(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
+void tcg_gen_gvec_4(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
+
+/* Expand a specific vector operation. */
+
+void tcg_gen_gvec_mov(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_not(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_neg(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+
+void tcg_gen_gvec_add(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_sub(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
+void tcg_gen_gvec_and(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_or(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_xor(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_andc(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_orc(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
+void tcg_gen_gvec_dup_mem(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t s, uint32_t m);
+void tcg_gen_gvec_dup_i32(TCGContext *, unsigned vece, uint32_t dofs, uint32_t s,
+ uint32_t m, TCGv_i32);
+void tcg_gen_gvec_dup_i64(TCGContext *, unsigned vece, uint32_t dofs, uint32_t s,
+ uint32_t m, TCGv_i64);
+
+void tcg_gen_gvec_dup8i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
+void tcg_gen_gvec_dup16i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
+void tcg_gen_gvec_dup32i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
+void tcg_gen_gvec_dup64i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
+
+/*
+ * 64-bit vector operations. Use these when the register has been allocated
+ * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
+ * OPRSZ = MAXSZ = 8.
+ */
+
+void tcg_gen_vec_neg8_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a);
+void tcg_gen_vec_neg16_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a);
+void tcg_gen_vec_neg32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a);
+
+void tcg_gen_vec_add8_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_add16_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_add32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+
+void tcg_gen_vec_sub8_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_sub16_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_sub32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
diff --git a/qemu/tcg/tcg-op-vec.c b/qemu/tcg/tcg-op-vec.c
index 1b9656ba..f923489c 100644
--- a/qemu/tcg/tcg-op-vec.c
+++ b/qemu/tcg/tcg-op-vec.c
@@ -73,7 +73,8 @@ static void vec_gen_op2(TCGContext *s, TCGOpcode opc, unsigned vece, TCGv_vec r,
TCGTemp *at = tcgv_vec_temp(s, a);
TCGType type = rt->base_type;
- tcg_debug_assert(at->base_type == type);
+ /* Must enough inputs for the output. */
+ tcg_debug_assert(at->base_type >= type);
vec_gen_2(s, opc, type, vece, temp_arg(rt), temp_arg(at));
}
@@ -85,8 +86,9 @@ static void vec_gen_op3(TCGContext *s, TCGOpcode opc, unsigned vece,
TCGTemp *bt = tcgv_vec_temp(s, b);
TCGType type = rt->base_type;
- tcg_debug_assert(at->base_type == type);
- tcg_debug_assert(bt->base_type == type);
+ /* Must enough inputs for the output. */
+ tcg_debug_assert(at->base_type >= type);
+ tcg_debug_assert(bt->base_type >= type);
vec_gen_3(s, opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
}
@@ -99,7 +101,7 @@ void tcg_gen_mov_vec(TCGContext *s, TCGv_vec r, TCGv_vec a)
#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
-static void tcg_gen_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
+static void do_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
{
TCGTemp *rt = tcgv_vec_temp(s, r);
vec_gen_2(s, INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
@@ -108,14 +110,14 @@ static void tcg_gen_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
TCGv_vec tcg_const_zeros_vec(TCGContext *s, TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(s, type);
- tcg_gen_dupi_vec(s, ret, MO_REG, 0);
+ do_dupi_vec(s, ret, MO_REG, 0);
return ret;
}
TCGv_vec tcg_const_ones_vec(TCGContext *s, TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(s, type);
- tcg_gen_dupi_vec(s, ret, MO_REG, -1);
+ do_dupi_vec(s, ret, MO_REG, -1);
return ret;
}
@@ -134,9 +136,9 @@ TCGv_vec tcg_const_ones_vec_matching(TCGContext *s, TCGv_vec m)
void tcg_gen_dup64i_vec(TCGContext *s, TCGv_vec r, uint64_t a)
{
if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
- tcg_gen_dupi_vec(s, r, MO_32, a);
+ do_dupi_vec(s, r, MO_32, a);
} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
- tcg_gen_dupi_vec(s, r, MO_64, a);
+ do_dupi_vec(s, r, MO_64, a);
} else {
TCGv_i64 c = tcg_const_i64(s, a);
tcg_gen_dup_i64_vec(s, MO_64, r, c);
@@ -146,17 +148,22 @@ void tcg_gen_dup64i_vec(TCGContext *s, TCGv_vec r, uint64_t a)
void tcg_gen_dup32i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
+ do_dupi_vec(s, r, MO_REG, dup_const(MO_32, a));
}
void tcg_gen_dup16i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
+ do_dupi_vec(s, r, MO_REG, dup_const(MO_16, a));
}
void tcg_gen_dup8i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
+ do_dupi_vec(s, r, MO_REG, dup_const(MO_8, a));
+}
+
+void tcg_gen_dupi_vec(TCGContext *s, unsigned vece, TCGv_vec r, uint64_t a)
+{
+ do_dupi_vec(s, r, MO_REG, dup_const(vece, a));
}
void tcg_gen_dup_i64_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i64 a)
@@ -167,14 +174,14 @@ void tcg_gen_dup_i64_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i64 a)
if (TCG_TARGET_REG_BITS == 64) {
TCGArg ai = tcgv_i64_arg(s, a);
- vec_gen_2(s, INDEX_op_dup_vec, type, MO_64, ri, ai);
+ vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
} else if (vece == MO_64) {
TCGArg al = tcgv_i32_arg(s, TCGV_LOW(s, a));
TCGArg ah = tcgv_i32_arg(s, TCGV_HIGH(s, a));
vec_gen_3(s, INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
} else {
TCGArg ai = tcgv_i32_arg(s, TCGV_LOW(s, a));
- vec_gen_2(s, INDEX_op_dup_vec, type, MO_64, ri, ai);
+ vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
}
}
diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h
index b7997d93..ef64065a 100644
--- a/qemu/tcg/tcg-op.h
+++ b/qemu/tcg/tcg-op.h
@@ -922,6 +922,7 @@ void tcg_gen_dup8i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup16i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup32i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup64i_vec(TCGContext *, TCGv_vec, uint64_t);
+void tcg_gen_dupi_vec(TCGContext *, unsigned vece, TCGv_vec, uint64_t);
void tcg_gen_add_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sub_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_and_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
diff --git a/qemu/tcg/tcg-opc.h b/qemu/tcg/tcg-opc.h
index 0a950118..c47fd966 100644
--- a/qemu/tcg/tcg-opc.h
+++ b/qemu/tcg/tcg-opc.h
@@ -232,6 +232,12 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
+
+#if TCG_TARGET_MAYBE_vec
+#include "tcg-target.opc.h"
+#endif
+
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
diff --git a/qemu/tcg/tcg-runtime.h b/qemu/tcg/tcg-runtime.h
index 7d75431d..9409651d 100644
--- a/qemu/tcg/tcg-runtime.h
+++ b/qemu/tcg/tcg-runtime.h
@@ -135,3 +135,33 @@ GEN_ATOMIC_HELPERS(xor_fetch)
GEN_ATOMIC_HELPERS(xchg)
#undef GEN_ATOMIC_HELPERS
+
+DEF_HELPER_FLAGS_3(gvec_mov, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_dup8, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup16, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup32, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup64, TCG_CALL_NO_RWG, void, ptr, i32, i64)
+
+DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c
index dc7e3785..1d95fe30 100644
--- a/qemu/tcg/tcg.c
+++ b/qemu/tcg/tcg.c
@@ -1060,10 +1060,10 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
- case NB_OPS:
- break;
+ default:
+ tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
+ return true;
}
- g_assert_not_reached();
}
/* Note: we convert the 64 bit args to 32 bit and do some alignment
@@ -3129,3 +3129,10 @@ void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
cpu_fprintf(f, "[TCG profiler not compiled]\n");
}
#endif
+
+#if !TCG_TARGET_MAYBE_vec
+void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...)
+{
+ g_assert_not_reached();
+}
+#endif
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index b4df7b97..da86b566 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -1094,7 +1094,7 @@ static inline TCGv_i64 tcg_temp_local_new_i64(TCGContext *s)
}
// UNICORN: Added
-#define TCG_OP_DEFS_TABLE_SIZE 151
+#define TCG_OP_DEFS_TABLE_SIZE 152
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
typedef struct TCGTargetOpDef {
@@ -1339,6 +1339,33 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi)
((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
#endif
+#if TCG_TARGET_MAYBE_vec
+/* Return zero if the tuple (opc, type, vece) is unsupportable;
+ return > 0 if it is directly supportable;
+ return < 0 if we must call tcg_expand_vec_op. */
+int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
+#else
+static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
+{
+ return 0;
+}
+#endif
+
+/* Expand the tuple (opc, type, vece) on the given arguments. */
+void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
+
+/* Replicate a constant C accoring to the log2 of the element size. */
+// Unicorn: renamed to avoid symbol clashing
+uint64_t dup_const_impl(unsigned vece, uint64_t c);
+
+#define dup_const(VECE, C) \
+ (__builtin_constant_p(VECE) \
+ ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
+ : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
+ : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
+ : dup_const_impl(VECE, C)) \
+ : dup_const_impl(VECE, C))
+
/*
* Memory helpers that will be used by TCG generated code.
*/
diff --git a/qemu/x86_64.h b/qemu/x86_64.h
index 8ad082cb..fbfb5a20 100644
--- a/qemu/x86_64.h
+++ b/qemu/x86_64.h
@@ -401,6 +401,7 @@
#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_x86_64
#define dummy_func dummy_func_x86_64
#define dummy_section dummy_section_x86_64
+#define dup_const_impl dup_const_impl_x86_64
#define end_list end_list_x86_64
#define ensure_writable_pages ensure_writable_pages_x86_64
#define eq128 eq128_x86_64
@@ -1608,6 +1609,29 @@
#define helper_get_cp_reg64 helper_get_cp_reg64_x86_64
#define helper_get_r13_banked helper_get_r13_banked_x86_64
#define helper_get_user_reg helper_get_user_reg_x86_64
+#define helper_gvec_add8 helper_gvec_add8_x86_64
+#define helper_gvec_add16 helper_gvec_add16_x86_64
+#define helper_gvec_add32 helper_gvec_add32_x86_64
+#define helper_gvec_add64 helper_gvec_add64_x86_64
+#define helper_gvec_and helper_gvec_and_x86_64
+#define helper_gvec_andc helper_gvec_andc_x86_64
+#define helper_gvec_dup8 helper_gvec_dup8_x86_64
+#define helper_gvec_dup16 helper_gvec_dup16_x86_64
+#define helper_gvec_dup32 helper_gvec_dup32_x86_64
+#define helper_gvec_dup64 helper_gvec_dup64_x86_64
+#define helper_gvec_mov helper_gvec_mov_x86_64
+#define helper_gvec_neg8 helper_gvec_neg8_x86_64
+#define helper_gvec_neg16 helper_gvec_neg16_x86_64
+#define helper_gvec_neg32 helper_gvec_neg32_x86_64
+#define helper_gvec_neg64 helper_gvec_neg64_x86_64
+#define helper_gvec_not helper_gvec_not_x86_64
+#define helper_gvec_or helper_gvec_or_x86_64
+#define helper_gvec_orc helper_gvec_orc_x86_64
+#define helper_gvec_sub8 helper_gvec_sub8_x86_64
+#define helper_gvec_sub16 helper_gvec_sub16_x86_64
+#define helper_gvec_sub32 helper_gvec_sub32_x86_64
+#define helper_gvec_sub64 helper_gvec_sub64_x86_64
+#define helper_gvec_xor helper_gvec_xor_x86_64
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_x86_64
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_x86_64
#define helper_iwmmxt_addcw helper_iwmmxt_addcw_x86_64
@@ -2830,6 +2854,7 @@
#define shifter_out_im shifter_out_im_x86_64
#define shortShift128Left shortShift128Left_x86_64
#define shortShift192Left shortShift192Left_x86_64
+#define simd_desc simd_desc_x86_64
#define simple_mpu_ap_bits simple_mpu_ap_bits_x86_64
#define size_code_gen_buffer size_code_gen_buffer_x86_64
#define softmmu_lock_user softmmu_lock_user_x86_64
@@ -2985,6 +3010,7 @@
#define tcg_enabled tcg_enabled_x86_64
#define tcg_exec_all tcg_exec_all_x86_64
#define tcg_exec_init tcg_exec_init_x86_64
+#define tcg_expand_vec_op tcg_expand_vec_op_x86_64
#define tcg_find_helper tcg_find_helper_x86_64
#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_x86_64
#define tcg_func_start tcg_func_start_x86_64
@@ -3062,6 +3088,7 @@
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_x86_64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_x86_64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_x86_64
+#define tcg_gen_dupi_vec tcg_gen_dupi_vec_x86_64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_x86_64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_x86_64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_x86_64
@@ -3086,6 +3113,33 @@
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_x86_64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64
#define tcg_gen_goto_tb tcg_gen_goto_tb_x86_64
+#define tcg_gen_gvec_2 tcg_gen_gvec_2_x86_64
+#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_x86_64
+#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_x86_64
+#define tcg_gen_gvec_3 tcg_gen_gvec_3_x86_64
+#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_x86_64
+#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_x86_64
+#define tcg_gen_gvec_4 tcg_gen_gvec_4_x86_64
+#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_x86_64
+#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_x86_64
+#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_x86_64
+#define tcg_gen_gvec_add tcg_gen_gvec_add_x86_64
+#define tcg_gen_gvec_and tcg_gen_gvec_and_x86_64
+#define tcg_gen_gvec_andc tcg_gen_gvec_andc_x86_64
+#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_x86_64
+#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_x86_64
+#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_x86_64
+#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_x86_64
+#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_x86_64
+#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_x86_64
+#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_x86_64
+#define tcg_gen_gvec_mov tcg_gen_gvec_mov_x86_64
+#define tcg_gen_gvec_neg tcg_gen_gvec_neg_x86_64
+#define tcg_gen_gvec_not tcg_gen_gvec_not_x86_64
+#define tcg_gen_gvec_or tcg_gen_gvec_or_x86_64
+#define tcg_gen_gvec_orc tcg_gen_gvec_orc_x86_64
+#define tcg_gen_gvec_sub tcg_gen_gvec_sub_x86_64
+#define tcg_gen_gvec_xor tcg_gen_gvec_xor_x86_64
#define tcg_gen_insn_start tcg_gen_insn_start_x86_64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_x86_64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_x86_64
@@ -3205,6 +3259,15 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64
+#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_x86_64
+#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_x86_64
+#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_x86_64
+#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_x86_64
+#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_x86_64
+#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_x86_64
+#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_x86_64
+#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_x86_64
+#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_x86_64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_x86_64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_x86_64
#define tcg_gen_xor_vec tcg_gen_xor_vec_x86_64