From 5e6196ea6b11fd45765eb19ecc018544facb483d Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Mon, 1 Mar 2021 19:00:19 -0500
Subject: [PATCH] target/riscv: Set instance_align on RISCVCPU TypeInfo

Fix alignment of CPURISCVState.vreg.

Backports 5de5b99b3101a1648ed583193db8d92eea0c4545
---
 qemu/target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c
index 73f379c7..f3a6c951 100644
--- a/qemu/target/riscv/cpu.c
+++ b/qemu/target/riscv/cpu.c
@@ -411,6 +411,7 @@ void riscv_cpu_register_types(void *opaque) {
         .parent = TYPE_CPU,
         .instance_userdata = opaque,
         .instance_size = sizeof(RISCVCPU),
+        .instance_align = __alignof__(RISCVCPU),
         .instance_init = riscv_cpu_init,
         .abstract = true,
         .class_size = sizeof(RISCVCPUClass),