From 5decf2e0edf23e25bae2208c9fd10b4d09307ec6 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Mon, 27 Aug 2018 04:16:24 -0400 Subject: [PATCH] target/mips: Add placeholder and invocation of decode_nanomips_opc() Add empty body and invocation of decode_nanomips_opc() if the bit ISA_NANOMIPS32 is set in ctx->insn_flags. Backports commit c533c0f4741be62501ef6c7f6ce77ffbfc2e4964 from qemu --- qemu/target/mips/translate.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index c7f22b1e..f86d6990 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -16696,6 +16696,19 @@ enum { NM_EVP = 0x01, }; + +/* + * + * nanoMIPS decoding engine + * + */ + +static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) +{ + return 2; +} + + /* SmartMIPS extension to MIPS32 */ #if defined(TARGET_MIPS64) @@ -21568,7 +21581,10 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } is_slot = ctx->hflags & MIPS_HFLAG_BMASK; - if (!(ctx->hflags & MIPS_HFLAG_M16)) { + if (ctx->insn_flags & ISA_NANOMIPS32) { + ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes = decode_nanomips_opc(env, ctx); + } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); insn_bytes = 4; decode_opc(env, ctx, &need_patch, &patch_offset);