From 5c7389680ec2a5810650272f7a1eaed8e9d643b7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 14 Feb 2018 02:05:44 -0500 Subject: [PATCH] target-arm: Implement YIELD insn to yield in ARM and Thumb translators Implement the YIELD instruction in the ARM and Thumb translators to actually yield control back to the top level loop rather than being a simple no-op. (We already do this for A64.) Backports commit c87e5a61c2b3024116f52f7e68273f864ff7ab82 from qemu --- qemu/target-arm/translate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index e28819f6..0836362f 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -4221,6 +4221,10 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + case 1: /* yield */ + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_YIELD; + break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_WFI; @@ -11699,6 +11703,9 @@ tb_end: case DISAS_WFE: gen_helper_wfe(tcg_ctx, tcg_ctx->cpu_env); break; + case DISAS_YIELD: + gen_helper_yield(tcg_ctx, tcg_ctx->cpu_env); + break; case DISAS_SWI: gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), default_exception_el(dc));