From 4b6a9ce61bd21c0acc9183153b8e90fa03ed287e Mon Sep 17 00:00:00 2001
From: Stefan Markovic <smarkovic@wavecomp.com>
Date: Fri, 17 Aug 2018 14:21:53 -0400
Subject: [PATCH] target/mips: Add CP0 BadInstrX register

Add CP0 BadInstrX register. This register will be used in nanoMIPS.

Backports commit 25beba9bf76a677747b779e997c6540677a38311 from qemu
---
 qemu/target/mips/cpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h
index 04a068b3..f83fef26 100644
--- a/qemu/target/mips/cpu.h
+++ b/qemu/target/mips/cpu.h
@@ -324,6 +324,7 @@ struct CPUMIPSState {
     target_ulong CP0_BadVAddr;
     uint32_t CP0_BadInstr;
     uint32_t CP0_BadInstrP;
+    uint32_t CP0_BadInstrX;
     int32_t CP0_Count;
     target_ulong CP0_EntryHi;
 #define CP0EnHi_EHINV 10