From 49cf18a8ff07ed483497aa8094202758d2ebea24 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sun, 11 Feb 2018 17:00:11 -0500 Subject: [PATCH] target-mips: Fix DisasContext's ulri member initialization Set DisasContext's ulri member to 0 or 1 as with other bool members. Backports commit 66991d1103562591eba6b801049720976317fe61 from qemu --- qemu/target-mips/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index 48faa5ae..53da7c8d 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -19289,7 +19289,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1; /* Restore delay slot state from the tb context. */ ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */ - ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI); + ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; restore_cpu_state(env, &ctx); #ifdef CONFIG_USER_ONLY ctx.mem_idx = MIPS_HFLAG_UM;