From 424b6eee4e33e86afc32f67a5f919506f809f429 Mon Sep 17 00:00:00 2001
From: Yongbok Kim <yongbok.kim@imgtec.com>
Date: Wed, 14 Feb 2018 16:55:21 -0500
Subject: [PATCH] target-mips: fix MIPS64R6-generic configuration

Fix core configuration for MIPS64R6-generic to make it as close as
I6400.
I6400 core has 48-bit of Virtual Address available (SEGBITS).
MIPS SIMD Architecture is available.
Rearrange order of bits to match the specification.

Backports commit 4dc89b782095d7a0b919fafd7b1322b3cb1279f1 from qemu
---
 qemu/target-mips/mips-defs.h      |  2 +-
 qemu/target-mips/translate_init.c | 19 ++++++++++---------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/qemu/target-mips/mips-defs.h b/qemu/target-mips/mips-defs.h
index 20aa87c2..53b185eb 100644
--- a/qemu/target-mips/mips-defs.h
+++ b/qemu/target-mips/mips-defs.h
@@ -11,7 +11,7 @@
 #if defined(TARGET_MIPS64)
 #define TARGET_LONG_BITS 64
 #define TARGET_PHYS_ADDR_SPACE_BITS 48
-#define TARGET_VIRT_ADDR_SPACE_BITS 42
+#define TARGET_VIRT_ADDR_SPACE_BITS 48
 #else
 #define TARGET_LONG_BITS 32
 #define TARGET_PHYS_ADDR_SPACE_BITS 40
diff --git a/qemu/target-mips/translate_init.c b/qemu/target-mips/translate_init.c
index fe97741d..4ebdb0d2 100644
--- a/qemu/target-mips/translate_init.c
+++ b/qemu/target-mips/translate_init.c
@@ -776,15 +776,16 @@ static const mips_def_t mips_defs[] =
                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
                        (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         MIPS_CONFIG2,
-        MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
-                       (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) |
-                       (1U << CP0C3_M),
-        MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
-                       (3 << CP0C4_IE) | (1 << CP0C4_M),
+        MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
+        MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
+                       (0xfc << CP0C4_KScrExist),
+        MIPS_CONFIG5 | (1 << CP0C5_LLB),
+        (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
+                             (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
         0,
         0,
-        (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
-        0,
         0,
         0,
         0,
@@ -797,13 +798,13 @@ static const mips_def_t mips_defs[] =
             (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
             (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
         0,
-        42,
+        48,
         48,
         0,0, 0,0, 0,0, 0,0, 0,0,
         (1 << CP0PG_ELPA),
         (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
                          (1U << CP0PG_RIE),
-        CPU_MIPS64R6,
+        CPU_MIPS64R6 | ASE_MSA,
         MMU_TYPE_R4000,
     },
     {