diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 494bbfc2..be96c6fb 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -3505,6 +3505,7 @@ mips_symbols = (
     'cpu_rddsp',
     'cpu_set_exception_base',
     'cpu_state_reset',
+    'cpu_supports_isa',
     'cpu_wrdsp',
     'do_raise_exception_err',
     'exception_resume_pc',
diff --git a/qemu/mips.h b/qemu/mips.h
index 0ee7dc58..74a56b37 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mips
 #define cpu_set_exception_base cpu_set_exception_base_mips
 #define cpu_state_reset cpu_state_reset_mips
+#define cpu_supports_isa cpu_supports_isa_mips
 #define cpu_wrdsp cpu_wrdsp_mips
 #define do_raise_exception_err do_raise_exception_err_mips
 #define exception_resume_pc exception_resume_pc_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index fe45132f..6c8d1dd1 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mips64
 #define cpu_set_exception_base cpu_set_exception_base_mips64
 #define cpu_state_reset cpu_state_reset_mips64
+#define cpu_supports_isa cpu_supports_isa_mips64
 #define cpu_wrdsp cpu_wrdsp_mips64
 #define do_raise_exception_err do_raise_exception_err_mips64
 #define exception_resume_pc exception_resume_pc_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 8f7a51f1..c88f1a84 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mips64el
 #define cpu_set_exception_base cpu_set_exception_base_mips64el
 #define cpu_state_reset cpu_state_reset_mips64el
+#define cpu_supports_isa cpu_supports_isa_mips64el
 #define cpu_wrdsp cpu_wrdsp_mips64el
 #define do_raise_exception_err do_raise_exception_err_mips64el
 #define exception_resume_pc exception_resume_pc_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index a407328b..8070f2bd 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mipsel
 #define cpu_set_exception_base cpu_set_exception_base_mipsel
 #define cpu_state_reset cpu_state_reset_mipsel
+#define cpu_supports_isa cpu_supports_isa_mipsel
 #define cpu_wrdsp cpu_wrdsp_mipsel
 #define do_raise_exception_err do_raise_exception_err_mipsel
 #define exception_resume_pc exception_resume_pc_mipsel
diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h
index 40bba8ee..f63519b9 100644
--- a/qemu/target/mips/cpu.h
+++ b/qemu/target/mips/cpu.h
@@ -807,6 +807,7 @@ int cpu_mips_exec(struct uc_struct *uc, CPUState *cpu);
 void mips_tcg_init(struct uc_struct *uc);
 MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model);
 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
 void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong address);
 
 /* TODO QOM'ify CPU reset and remove */
diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index b866d334..c17b9dc9 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -20367,6 +20367,16 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model)
     return cpu;
 }
 
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
+{
+    const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
+    if (!def) {
+        return false;
+    }
+
+    return (def->insn_flags & isa) != 0;
+}
+
 void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong address)
 {
     MIPSCPU *vp = MIPS_CPU(uc, qemu_get_cpu(uc, vp_index));