target/riscv: Add the Hypervisor extension

Backports commit af1fa0039c799a350bcde07b3d8a71dfde07d11b from qemu

qemu/target/riscv/cpu.h

@@ -71,6 +71,7 @@
 #define RVC RV('C')
 #define RVS RV('S')
 #define RVU RV('U')
+#define RVH RV('H')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there