diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index ed727f60..b17ca86b 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -4373,7 +4373,6 @@ sparc_symbols = (
     'cpu_sparc_set_id',
     'dump_mmu',
     'gen_intermediate_code_init',
-    'helper_cas_asi',
     'helper_check_align',
     'helper_check_ieee_exceptions',
     'helper_compute_C_icc',
diff --git a/qemu/sparc.h b/qemu/sparc.h
index 2f55d01d..3bc48337 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -3359,7 +3359,6 @@
 #define cpu_sparc_set_id cpu_sparc_set_id_sparc
 #define dump_mmu dump_mmu_sparc
 #define gen_intermediate_code_init gen_intermediate_code_init_sparc
-#define helper_cas_asi helper_cas_asi_sparc
 #define helper_check_align helper_check_align_sparc
 #define helper_check_ieee_exceptions helper_check_ieee_exceptions_sparc
 #define helper_compute_C_icc helper_compute_C_icc_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index b8c05a31..aa44f725 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -3359,7 +3359,6 @@
 #define cpu_sparc_set_id cpu_sparc_set_id_sparc64
 #define dump_mmu dump_mmu_sparc64
 #define gen_intermediate_code_init gen_intermediate_code_init_sparc64
-#define helper_cas_asi helper_cas_asi_sparc64
 #define helper_check_align helper_check_align_sparc64
 #define helper_check_ieee_exceptions helper_check_ieee_exceptions_sparc64
 #define helper_compute_C_icc helper_compute_C_icc_sparc64
diff --git a/qemu/target-sparc/helper.h b/qemu/target-sparc/helper.h
index 060d4226..a926fd34 100644
--- a/qemu/target-sparc/helper.h
+++ b/qemu/target-sparc/helper.h
@@ -20,7 +20,6 @@ DEF_HELPER_2(wrcwp, void, env, tl)
 DEF_HELPER_FLAGS_2(array8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_1(popc, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_3(ldda_asi, TCG_CALL_NO_WG, void, env, tl, int)
-DEF_HELPER_FLAGS_5(casx_asi, TCG_CALL_NO_WG, tl, env, tl, tl, tl, i32)
 DEF_HELPER_FLAGS_2(set_softint, TCG_CALL_NO_RWG, void, env, i64)
 DEF_HELPER_FLAGS_2(clear_softint, TCG_CALL_NO_RWG, void, env, i64)
 DEF_HELPER_FLAGS_2(write_softint, TCG_CALL_NO_RWG, void, env, i64)
@@ -28,9 +27,6 @@ DEF_HELPER_FLAGS_2(tick_set_count, TCG_CALL_NO_RWG, void, ptr, i64)
 DEF_HELPER_FLAGS_3(tick_get_count, TCG_CALL_NO_WG, i64, env, ptr, int)
 DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void, ptr, i64)
 #endif
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
-DEF_HELPER_FLAGS_5(cas_asi, TCG_CALL_NO_WG, tl, env, tl, tl, tl, i32)
-#endif
 DEF_HELPER_FLAGS_3(check_align, TCG_CALL_NO_WG, void, env, tl, i32)
 DEF_HELPER_1(debug, void, env)
 DEF_HELPER_1(save, void, env)
diff --git a/qemu/target-sparc/ldst_helper.c b/qemu/target-sparc/ldst_helper.c
index 23de74f5..3cbcc367 100644
--- a/qemu/target-sparc/ldst_helper.c
+++ b/qemu/target-sparc/ldst_helper.c
@@ -2156,37 +2156,8 @@ void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi)
     QT0.high = h;
     QT0.low = l;
 }
-
-target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
-                             target_ulong val1, target_ulong val2,
-                             uint32_t asi)
-{
-    target_ulong ret;
-
-    ret = helper_ld_asi(env, addr, asi, MO_Q);
-    if (val2 == ret) {
-        helper_st_asi(env, addr, val1, asi, MO_Q);
-    }
-    return ret;
-}
 #endif /* TARGET_SPARC64 */
 
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
-target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
-                            target_ulong val1, target_ulong val2, uint32_t asi)
-{
-    target_ulong ret;
-
-    val2 &= 0xffffffffUL;
-    ret = helper_ld_asi(env, addr, asi, MO_UL);
-    ret &= 0xffffffffUL;
-    if (val2 == ret) {
-        helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, MO_UL);
-    }
-    return ret;
-}
-#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
-
 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
 {
     /* XXX add 128 bit load */
diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c
index 2bbe846f..e08f93de 100644
--- a/qemu/target-sparc/translate.c
+++ b/qemu/target-sparc/translate.c
@@ -2491,25 +2491,38 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
     }
 }
 
-static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
+static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpr,
                         int insn, int rd)
 {
     TCGContext *tcg_ctx = dc->uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, MO_TEUL);
-    TCGv val1, dst;
-    TCGv_i32 r_asi;
+    TCGv cmpv, oldv, tmpv;
 
-    if (da.type == GET_ASI_EXCP) {
+    switch (da.type) {
+    case GET_ASI_EXCP:
         return;
-    }
+    case GET_ASI_DIRECT:
+        cmpv = tcg_temp_new(tcg_ctx);
+        oldv = tcg_temp_new(tcg_ctx);
+        tmpv = tcg_temp_new(tcg_ctx);
+        tcg_gen_ext32u_tl(tcg_ctx, cmpv, cmpr);
 
-    save_state(dc);
-    val1 = gen_load_gpr(dc, rd);
-    dst = gen_dest_gpr(dc, rd);
-    r_asi = tcg_const_i32(tcg_ctx, da.asi);
-    gen_helper_cas_asi(tcg_ctx, dst, tcg_ctx->cpu_env, addr, val1, val2, r_asi);
-    tcg_temp_free_i32(tcg_ctx, r_asi);
-    gen_store_gpr(dc, rd, dst);
+        /* ??? Should be atomic.  */
+        tcg_gen_qemu_ld_tl(dc->uc, oldv, addr, da.mem_idx, da.memop);
+        tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, tmpv, oldv, cmpv,
+                           gen_load_gpr(dc, rd), oldv);
+        tcg_gen_qemu_st_tl(dc->uc, tmpv, addr, da.mem_idx, da.memop);
+
+        gen_store_gpr(dc, rd, oldv);
+        tcg_temp_free(tcg_ctx, cmpv);
+        tcg_temp_free(tcg_ctx, oldv);
+        tcg_temp_free(tcg_ctx, tmpv);
+        break;
+    default:
+        /* ??? Should be DAE_invalid_asi.  */
+        gen_exception(dc, TT_DATA_ACCESS);
+        break;
+    }
 }
 
 static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
@@ -2829,25 +2842,35 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
     }
 }
 
-static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
+static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
                          int insn, int rd)
 {
     TCGContext *tcg_ctx = dc->uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, MO_TEQ);
-    TCGv val1 = gen_load_gpr(dc, rd);
-    TCGv dst = gen_dest_gpr(dc, rd);
-    TCGv_i32 r_asi;
+    TCGv oldv, tmpv;
 
-    if (da.type == GET_ASI_EXCP) {
+    switch (da.type) {
+    case GET_ASI_EXCP:
         return;
+    case GET_ASI_DIRECT:
+        oldv = tcg_temp_new(tcg_ctx);
+        tmpv = tcg_temp_new(tcg_ctx);
+
+        /* ??? Should be atomic.  */
+        tcg_gen_qemu_ld_tl(dc->uc, oldv, addr, da.mem_idx, da.memop);
+        tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, tmpv, oldv, cmpv,
+                           gen_load_gpr(dc, rd), oldv);
+        tcg_gen_qemu_st_tl(dc->uc, tmpv, addr, da.mem_idx, da.memop);
+
+        gen_store_gpr(dc, rd, oldv);
+        tcg_temp_free(tcg_ctx, oldv);
+        tcg_temp_free(tcg_ctx, tmpv);
+        break;
+    default:
+        /* ??? Should be DAE_invalid_asi.  */
+        gen_exception(dc, TT_DATA_ACCESS);
+        break;
     }
-
-    save_state(dc);
-    r_asi = tcg_const_i32(tcg_ctx, da.asi);
-
-    gen_helper_casx_asi(tcg_ctx, dst, tcg_ctx->cpu_env, addr, val1, val2, r_asi);
-    tcg_temp_free_i32(tcg_ctx, r_asi);
-    gen_store_gpr(dc, rd, dst);
 }
 
 #elif !defined(CONFIG_USER_ONLY)