diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h index c7711d7f..305f4d16 100644 --- a/qemu/target/mips/cpu.h +++ b/qemu/target/mips/cpu.h @@ -233,38 +233,152 @@ typedef struct mips_def_t mips_def_t; * 7 TagLo TagHi KScratch * */ -#define CPO_REGISTER_00 0 -#define CPO_REGISTER_01 1 -#define CPO_REGISTER_02 2 -#define CPO_REGISTER_03 3 -#define CPO_REGISTER_04 4 -#define CPO_REGISTER_05 5 -#define CPO_REGISTER_06 6 -#define CPO_REGISTER_07 7 -#define CPO_REGISTER_08 8 -#define CPO_REGISTER_09 9 -#define CPO_REGISTER_10 10 -#define CPO_REGISTER_11 11 -#define CPO_REGISTER_12 12 -#define CPO_REGISTER_13 13 -#define CPO_REGISTER_14 14 -#define CPO_REGISTER_15 15 -#define CPO_REGISTER_16 16 -#define CPO_REGISTER_17 17 -#define CPO_REGISTER_18 18 -#define CPO_REGISTER_19 19 -#define CPO_REGISTER_20 20 -#define CPO_REGISTER_21 21 -#define CPO_REGISTER_22 22 -#define CPO_REGISTER_23 23 -#define CPO_REGISTER_24 24 -#define CPO_REGISTER_25 25 -#define CPO_REGISTER_26 26 -#define CPO_REGISTER_27 27 -#define CPO_REGISTER_28 28 -#define CPO_REGISTER_29 29 -#define CPO_REGISTER_30 30 -#define CPO_REGISTER_31 31 +#define CP0_REGISTER_00 0 +#define CP0_REGISTER_01 1 +#define CP0_REGISTER_02 2 +#define CP0_REGISTER_03 3 +#define CP0_REGISTER_04 4 +#define CP0_REGISTER_05 5 +#define CP0_REGISTER_06 6 +#define CP0_REGISTER_07 7 +#define CP0_REGISTER_08 8 +#define CP0_REGISTER_09 9 +#define CP0_REGISTER_10 10 +#define CP0_REGISTER_11 11 +#define CP0_REGISTER_12 12 +#define CP0_REGISTER_13 13 +#define CP0_REGISTER_14 14 +#define CP0_REGISTER_15 15 +#define CP0_REGISTER_16 16 +#define CP0_REGISTER_17 17 +#define CP0_REGISTER_18 18 +#define CP0_REGISTER_19 19 +#define CP0_REGISTER_20 20 +#define CP0_REGISTER_21 21 +#define CP0_REGISTER_22 22 +#define CP0_REGISTER_23 23 +#define CP0_REGISTER_24 24 +#define CP0_REGISTER_25 25 +#define CP0_REGISTER_26 26 +#define CP0_REGISTER_27 27 +#define CP0_REGISTER_28 28 +#define CP0_REGISTER_29 29 +#define CP0_REGISTER_30 30 +#define CP0_REGISTER_31 31 + + +/* CP0 Register 00 */ +#define CP0_REG00__INDEX 0 +#define CP0_REG00__VPCONTROL 4 +/* CP0 Register 01 */ +/* CP0 Register 02 */ +#define CP0_REG02__ENTRYLO0 0 +/* CP0 Register 03 */ +#define CP0_REG03__ENTRYLO1 0 +#define CP0_REG03__GLOBALNUM 1 +/* CP0 Register 04 */ +#define CP0_REG04__CONTEXT 0 +#define CP0_REG04__USERLOCAL 2 +#define CP0_REG04__DBGCONTEXTID 4 +#define CP0_REG00__MMID 5 +/* CP0 Register 05 */ +#define CP0_REG05__PAGEMASK 0 +#define CP0_REG05__PAGEGRAIN 1 +/* CP0 Register 06 */ +#define CP0_REG06__WIRED 0 +/* CP0 Register 07 */ +#define CP0_REG07__HWRENA 0 +/* CP0 Register 08 */ +#define CP0_REG08__BADVADDR 0 +#define CP0_REG08__BADINSTR 1 +#define CP0_REG08__BADINSTRP 2 +/* CP0 Register 09 */ +#define CP0_REG09__COUNT 0 +#define CP0_REG09__SAARI 6 +#define CP0_REG09__SAAR 7 +/* CP0 Register 10 */ +#define CP0_REG10__ENTRYHI 0 +#define CP0_REG10__GUESTCTL1 4 +#define CP0_REG10__GUESTCTL2 5 +/* CP0 Register 11 */ +#define CP0_REG11__COMPARE 0 +#define CP0_REG11__GUESTCTL0EXT 4 +/* CP0 Register 12 */ +#define CP0_REG12__STATUS 0 +#define CP0_REG12__INTCTL 1 +#define CP0_REG12__SRSCTL 2 +#define CP0_REG12__GUESTCTL0 6 +#define CP0_REG12__GTOFFSET 7 +/* CP0 Register 13 */ +#define CP0_REG13__CAUSE 0 +/* CP0 Register 14 */ +#define CP0_REG14__EPC 0 +/* CP0 Register 15 */ +#define CP0_REG15__PRID 0 +#define CP0_REG15__EBASE 1 +#define CP0_REG15__CDMMBASE 2 +#define CP0_REG15__CMGCRBASE 3 +/* CP0 Register 16 */ +#define CP0_REG16__CONFIG 0 +#define CP0_REG16__CONFIG1 1 +#define CP0_REG16__CONFIG2 2 +#define CP0_REG16__CONFIG3 3 +#define CP0_REG16__CONFIG4 4 +#define CP0_REG16__CONFIG5 5 +#define CP0_REG00__CONFIG7 7 +/* CP0 Register 17 */ +#define CP0_REG17__LLADDR 0 +#define CP0_REG17__MAAR 1 +#define CP0_REG17__MAARI 2 +/* CP0 Register 18 */ +#define CP0_REG18__WATCHLO0 0 +#define CP0_REG18__WATCHLO1 1 +#define CP0_REG18__WATCHLO2 2 +#define CP0_REG18__WATCHLO3 3 +/* CP0 Register 19 */ +#define CP0_REG19__WATCHHI0 0 +#define CP0_REG19__WATCHHI1 1 +#define CP0_REG19__WATCHHI2 2 +#define CP0_REG19__WATCHHI3 3 +/* CP0 Register 20 */ +#define CP0_REG20__XCONTEXT 0 +/* CP0 Register 21 */ +/* CP0 Register 22 */ +/* CP0 Register 23 */ +#define CP0_REG23__DEBUG 0 +/* CP0 Register 24 */ +#define CP0_REG24__DEPC 0 +/* CP0 Register 25 */ +#define CP0_REG25__PERFCTL0 0 +#define CP0_REG25__PERFCNT0 1 +#define CP0_REG25__PERFCTL1 2 +#define CP0_REG25__PERFCNT1 3 +#define CP0_REG25__PERFCTL2 4 +#define CP0_REG25__PERFCNT2 5 +#define CP0_REG25__PERFCTL3 6 +#define CP0_REG25__PERFCNT3 7 +/* CP0 Register 26 */ +#define CP0_REG00__ERRCTL 0 +/* CP0 Register 27 */ +#define CP0_REG27__CACHERR 0 +/* CP0 Register 28 */ +#define CP0_REG28__ITAGLO 0 +#define CP0_REG28__IDATALO 1 +#define CP0_REG28__DTAGLO 2 +#define CP0_REG28__DDATALO 3 +/* CP0 Register 29 */ +#define CP0_REG29__IDATAHI 1 +#define CP0_REG29__DDATAHI 3 +/* CP0 Register 30 */ +#define CP0_REG30__ERROREPC 0 +/* CP0 Register 31 */ +#define CP0_REG31__DESAVE 0 +#define CP0_REG31__KSCRATCH1 2 +#define CP0_REG31__KSCRATCH2 3 +#define CP0_REG31__KSCRATCH3 4 +#define CP0_REG31__KSCRATCH4 5 +#define CP0_REG31__KSCRATCH5 6 +#define CP0_REG31__KSCRATCH6 7 typedef struct TCState TCState; diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index c4c4296e..b877972d 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -6659,7 +6659,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *rn = "invalid"; switch (reg) { - case CPO_REGISTER_02: + case CP0_REGISTER_02: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6670,7 +6670,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_03: + case CP0_REGISTER_03: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6681,7 +6681,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_09: + case CP0_REGISTER_09: switch (sel) { case 7: CP0_CHECK(ctx->saar); @@ -6692,7 +6692,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_17: + case CP0_REGISTER_17: switch (sel) { case 0: gen_mfhc0_load64(ctx, arg, offsetof(CPUMIPSState, lladdr), @@ -6708,7 +6708,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_28: + case CP0_REGISTER_28: switch (sel) { case 0: case 2: @@ -6741,7 +6741,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) uint64_t mask = ctx->PAMask >> 36; switch (reg) { - case CPO_REGISTER_02: + case CP0_REGISTER_02: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6753,7 +6753,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_03: + case CP0_REGISTER_03: switch (sel) { case 0: CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); @@ -6765,7 +6765,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_09: + case CP0_REGISTER_09: switch (sel) { case 7: CP0_CHECK(ctx->saar); @@ -6775,7 +6775,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) default: goto cp0_unimplemented; } - case CPO_REGISTER_17: + case CP0_REGISTER_17: switch (sel) { case 0: /* LLAddr is read-only (the only exception is bit 0 if LLB is @@ -6793,7 +6793,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_28: + case CP0_REGISTER_28: switch (sel) { case 0: case 2: @@ -6835,7 +6835,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) check_insn(ctx, ISA_MIPS32); switch (reg) { - case CPO_REGISTER_00: + case CP0_REGISTER_00: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Index)); @@ -6865,7 +6865,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_01: + case CP0_REGISTER_01: switch (sel) { case 0: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); @@ -6911,7 +6911,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_02: + case CP0_REGISTER_02: switch (sel) { case 0: { @@ -6969,7 +6969,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_03: + case CP0_REGISTER_03: switch (sel) { case 0: { @@ -6997,7 +6997,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_04: + case CP0_REGISTER_04: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_Context)); @@ -7019,7 +7019,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_05: + case CP0_REGISTER_05: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PageMask)); @@ -7066,7 +7066,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_06: + case CP0_REGISTER_06: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Wired)); @@ -7106,7 +7106,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_07: + case CP0_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -7117,7 +7117,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_08: + case CP0_REGISTER_08: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); @@ -7138,7 +7138,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_09: + case CP0_REGISTER_09: switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ @@ -7170,7 +7170,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_10: + case CP0_REGISTER_10: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi)); @@ -7181,7 +7181,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_11: + case CP0_REGISTER_11: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Compare)); @@ -7192,7 +7192,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_12: + case CP0_REGISTER_12: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Status)); @@ -7217,7 +7217,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_13: + case CP0_REGISTER_13: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Cause)); @@ -7227,7 +7227,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_14: + case CP0_REGISTER_14: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -7238,7 +7238,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_15: + case CP0_REGISTER_15: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PRid)); @@ -7261,7 +7261,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_16: + case CP0_REGISTER_16: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config0)); @@ -7300,7 +7300,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_17: + case CP0_REGISTER_17: switch (sel) { case 0: gen_helper_mfc0_lladdr(tcg_ctx, arg, tcg_ctx->cpu_env); @@ -7320,7 +7320,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_18: + case CP0_REGISTER_18: switch (sel) { case 0: case 1: @@ -7338,7 +7338,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_19: + case CP0_REGISTER_19: switch (sel) { case 0: case 1: @@ -7356,7 +7356,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_20: + case CP0_REGISTER_20: switch (sel) { case 0: #if defined(TARGET_MIPS64) @@ -7370,7 +7370,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_21: + case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -7382,11 +7382,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_22: + case CP0_REGISTER_22: tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */ rn = "'Diagnostic"; /* implementation dependent */ break; - case CPO_REGISTER_23: + case CP0_REGISTER_23: switch (sel) { case 0: gen_helper_mfc0_debug(tcg_ctx, arg, tcg_ctx->cpu_env); /* EJTAG support */ @@ -7412,7 +7412,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_24: + case CP0_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -7424,7 +7424,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_25: + case CP0_REGISTER_25: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Performance0)); @@ -7462,7 +7462,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_26: + case CP0_REGISTER_26: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_ErrCtl)); @@ -7472,7 +7472,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_27: + case CP0_REGISTER_27: switch (sel) { case 0: case 1: @@ -7485,7 +7485,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_28: + case CP0_REGISTER_28: switch (sel) { case 0: case 2: @@ -7510,7 +7510,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_29: + case CP0_REGISTER_29: switch (sel) { case 0: case 2: @@ -7530,7 +7530,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_30: + case CP0_REGISTER_30: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); @@ -7541,7 +7541,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_31: + case CP0_REGISTER_31: switch (sel) { case 0: /* EJTAG support */ @@ -7589,7 +7589,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) //} switch (reg) { - case CPO_REGISTER_00: + case CP0_REGISTER_00: switch (sel) { case 0: gen_helper_mtc0_index(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7619,7 +7619,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_01: + case CP0_REGISTER_01: switch (sel) { case 0: /* ignored */ @@ -7666,7 +7666,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_02: + case CP0_REGISTER_02: switch (sel) { case 0: gen_helper_mtc0_entrylo0(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7711,7 +7711,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_03: + case CP0_REGISTER_03: switch (sel) { case 0: gen_helper_mtc0_entrylo1(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7726,7 +7726,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_04: + case CP0_REGISTER_04: switch (sel) { case 0: gen_helper_mtc0_context(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7746,7 +7746,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_05: + case CP0_REGISTER_05: switch (sel) { case 0: gen_helper_mtc0_pagemask(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7792,7 +7792,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_06: + case CP0_REGISTER_06: switch (sel) { case 0: gen_helper_mtc0_wired(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7832,7 +7832,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_07: + case CP0_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -7844,7 +7844,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_08: + case CP0_REGISTER_08: switch (sel) { case 0: /* ignored */ @@ -7862,7 +7862,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_09: + case CP0_REGISTER_09: switch (sel) { case 0: gen_helper_mtc0_count(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7882,7 +7882,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_10: + case CP0_REGISTER_10: switch (sel) { case 0: gen_helper_mtc0_entryhi(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7892,7 +7892,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_11: + case CP0_REGISTER_11: switch (sel) { case 0: gen_helper_mtc0_compare(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -7903,7 +7903,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_12: + case CP0_REGISTER_12: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -7938,7 +7938,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_13: + case CP0_REGISTER_13: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -7954,7 +7954,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_14: + case CP0_REGISTER_14: switch (sel) { case 0: tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -7964,7 +7964,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_15: + case CP0_REGISTER_15: switch (sel) { case 0: /* ignored */ @@ -7979,7 +7979,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_16: + case CP0_REGISTER_16: switch (sel) { case 0: gen_helper_mtc0_config0(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -8028,7 +8028,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_17: + case CP0_REGISTER_17: switch (sel) { case 0: gen_helper_mtc0_lladdr(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -8048,7 +8048,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_18: + case CP0_REGISTER_18: switch (sel) { case 0: case 1: @@ -8066,7 +8066,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_19: + case CP0_REGISTER_19: switch (sel) { case 0: case 1: @@ -8084,7 +8084,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_20: + case CP0_REGISTER_20: switch (sel) { case 0: #if defined(TARGET_MIPS64) @@ -8097,7 +8097,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_21: + case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -8109,11 +8109,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_22: + case CP0_REGISTER_22: /* ignored */ rn = "Diagnostic"; /* implementation dependent */ break; - case CPO_REGISTER_23: + case CP0_REGISTER_23: switch (sel) { case 0: gen_helper_mtc0_debug(tcg_ctx, tcg_ctx->cpu_env, arg); /* EJTAG support */ @@ -8152,7 +8152,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_24: + case CP0_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -8163,7 +8163,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_25: + case CP0_REGISTER_25: switch (sel) { case 0: gen_helper_mtc0_performance0(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -8201,7 +8201,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_26: + case CP0_REGISTER_26: switch (sel) { case 0: gen_helper_mtc0_errctl(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -8212,7 +8212,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_27: + case CP0_REGISTER_27: switch (sel) { case 0: case 1: @@ -8225,7 +8225,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_28: + case CP0_REGISTER_28: switch (sel) { case 0: case 2: @@ -8245,7 +8245,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_29: + case CP0_REGISTER_29: switch (sel) { case 0: case 2: @@ -8266,7 +8266,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_30: + case CP0_REGISTER_30: switch (sel) { case 0: tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); @@ -8276,7 +8276,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_31: + case CP0_REGISTER_31: switch (sel) { case 0: /* EJTAG support */ @@ -8327,7 +8327,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) check_insn(ctx, ISA_MIPS64); switch (reg) { - case CPO_REGISTER_00: + case CP0_REGISTER_00: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Index)); @@ -8357,7 +8357,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_01: + case CP0_REGISTER_01: switch (sel) { case 0: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); @@ -8403,7 +8403,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_02: + case CP0_REGISTER_02: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0)); @@ -8448,7 +8448,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_03: + case CP0_REGISTER_03: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); @@ -8463,7 +8463,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_04: + case CP0_REGISTER_04: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_Context)); @@ -8483,7 +8483,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_05: + case CP0_REGISTER_05: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PageMask)); @@ -8528,7 +8528,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_06: + case CP0_REGISTER_06: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Wired)); @@ -8568,7 +8568,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_07: + case CP0_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -8579,7 +8579,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_08: + case CP0_REGISTER_08: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); @@ -8599,7 +8599,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_09: + case CP0_REGISTER_09: switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ @@ -8631,7 +8631,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_10: + case CP0_REGISTER_10: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi)); @@ -8641,7 +8641,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_11: + case CP0_REGISTER_11: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Compare)); @@ -8652,7 +8652,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_12: + case CP0_REGISTER_12: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Status)); @@ -8677,7 +8677,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_13: + case CP0_REGISTER_13: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Cause)); @@ -8687,7 +8687,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_14: + case CP0_REGISTER_14: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -8697,7 +8697,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_15: + case CP0_REGISTER_15: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PRid)); @@ -8718,7 +8718,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_16: + case CP0_REGISTER_16: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config0)); @@ -8757,7 +8757,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_17: + case CP0_REGISTER_17: switch (sel) { case 0: gen_helper_dmfc0_lladdr(tcg_ctx, arg, tcg_ctx->cpu_env); @@ -8777,7 +8777,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_18: + case CP0_REGISTER_18: switch (sel) { case 0: case 1: @@ -8795,7 +8795,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_19: + case CP0_REGISTER_19: switch (sel) { case 0: case 1: @@ -8813,7 +8813,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_20: + case CP0_REGISTER_20: switch (sel) { case 0: check_insn(ctx, ISA_MIPS3); @@ -8824,7 +8824,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_21: + case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -8836,11 +8836,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_22: + case CP0_REGISTER_22: tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */ rn = "'Diagnostic"; /* implementation dependent */ break; - case CPO_REGISTER_23: + case CP0_REGISTER_23: switch (sel) { case 0: gen_helper_mfc0_debug(tcg_ctx, arg, tcg_ctx->cpu_env); /* EJTAG support */ @@ -8866,7 +8866,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_24: + case CP0_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -8877,7 +8877,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_25: + case CP0_REGISTER_25: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Performance0)); @@ -8915,7 +8915,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_26: + case CP0_REGISTER_26: switch (sel) { case 0: gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_ErrCtl)); @@ -8925,7 +8925,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_27: + case CP0_REGISTER_27: switch (sel) { /* ignored */ case 0: @@ -8939,7 +8939,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_28: + case CP0_REGISTER_28: switch (sel) { case 0: case 2: @@ -8959,7 +8959,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_29: + case CP0_REGISTER_29: switch (sel) { case 0: case 2: @@ -8979,7 +8979,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_30: + case CP0_REGISTER_30: switch (sel) { case 0: tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); @@ -8989,7 +8989,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_31: + case CP0_REGISTER_31: switch (sel) { case 0: /* EJTAG support */ @@ -9036,7 +9036,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) //} switch (reg) { - case CPO_REGISTER_00: + case CP0_REGISTER_00: switch (sel) { case 0: gen_helper_mtc0_index(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9066,7 +9066,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_01: + case CP0_REGISTER_01: switch (sel) { case 0: /* ignored */ @@ -9111,7 +9111,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_02: + case CP0_REGISTER_02: switch (sel) { case 0: gen_helper_dmtc0_entrylo0(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9156,7 +9156,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_03: + case CP0_REGISTER_03: switch (sel) { case 0: gen_helper_dmtc0_entrylo1(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9171,7 +9171,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_04: + case CP0_REGISTER_04: switch (sel) { case 0: gen_helper_mtc0_context(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9191,7 +9191,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_05: + case CP0_REGISTER_05: switch (sel) { case 0: gen_helper_mtc0_pagemask(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9236,7 +9236,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_06: + case CP0_REGISTER_06: switch (sel) { case 0: gen_helper_mtc0_wired(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9276,7 +9276,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_07: + case CP0_REGISTER_07: switch (sel) { case 0: check_insn(ctx, ISA_MIPS32R2); @@ -9288,7 +9288,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_08: + case CP0_REGISTER_08: switch (sel) { case 0: /* ignored */ @@ -9306,7 +9306,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_09: + case CP0_REGISTER_09: switch (sel) { case 0: gen_helper_mtc0_count(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9328,7 +9328,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; break; - case CPO_REGISTER_10: + case CP0_REGISTER_10: switch (sel) { case 0: gen_helper_mtc0_entryhi(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9338,7 +9338,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_11: + case CP0_REGISTER_11: switch (sel) { case 0: gen_helper_mtc0_compare(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9351,7 +9351,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; break; - case CPO_REGISTER_12: + case CP0_REGISTER_12: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -9386,7 +9386,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_13: + case CP0_REGISTER_13: switch (sel) { case 0: save_cpu_state(ctx, 1); @@ -9402,7 +9402,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_14: + case CP0_REGISTER_14: switch (sel) { case 0: tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC)); @@ -9412,7 +9412,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_15: + case CP0_REGISTER_15: switch (sel) { case 0: /* ignored */ @@ -9427,7 +9427,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_16: + case CP0_REGISTER_16: switch (sel) { case 0: gen_helper_mtc0_config0(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9467,7 +9467,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_17: + case CP0_REGISTER_17: switch (sel) { case 0: gen_helper_mtc0_lladdr(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9487,7 +9487,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_18: + case CP0_REGISTER_18: switch (sel) { case 0: case 1: @@ -9505,7 +9505,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_19: + case CP0_REGISTER_19: switch (sel) { case 0: case 1: @@ -9523,7 +9523,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_20: + case CP0_REGISTER_20: switch (sel) { case 0: check_insn(ctx, ISA_MIPS3); @@ -9534,7 +9534,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_21: + case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { @@ -9546,11 +9546,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_22: + case CP0_REGISTER_22: /* ignored */ rn = "Diagnostic"; /* implementation dependent */ break; - case CPO_REGISTER_23: + case CP0_REGISTER_23: switch (sel) { case 0: gen_helper_mtc0_debug(tcg_ctx, tcg_ctx->cpu_env, arg); /* EJTAG support */ @@ -9587,7 +9587,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_24: + case CP0_REGISTER_24: switch (sel) { case 0: /* EJTAG support */ @@ -9598,7 +9598,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_25: + case CP0_REGISTER_25: switch (sel) { case 0: gen_helper_mtc0_performance0(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9636,7 +9636,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_26: + case CP0_REGISTER_26: switch (sel) { case 0: gen_helper_mtc0_errctl(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -9647,7 +9647,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_27: + case CP0_REGISTER_27: switch (sel) { case 0: case 1: @@ -9660,7 +9660,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_28: + case CP0_REGISTER_28: switch (sel) { case 0: case 2: @@ -9680,7 +9680,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_29: + case CP0_REGISTER_29: switch (sel) { case 0: case 2: @@ -9701,7 +9701,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_30: + case CP0_REGISTER_30: switch (sel) { case 0: tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); @@ -9711,7 +9711,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CPO_REGISTER_31: + case CP0_REGISTER_31: switch (sel) { case 0: /* EJTAG support */