From 38f0e31950730bb035951d6bfc004bc412cf78ec Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Mon, 18 Nov 2019 22:55:21 -0500 Subject: [PATCH] target/mips: Clean up handling of CP0 register 7 Clean up handling of CP0 register 7. Backports commit 143a9875e51a358924154ffa76135ca29415dfb5 from qemu --- qemu/target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 79792513..4f0cc8bb 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -7168,7 +7168,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name = "HWREna"; @@ -7898,7 +7898,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(tcg_ctx, tcg_ctx->cpu_env, arg); ctx->base.is_jmp = DISAS_STOP; @@ -8638,7 +8638,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name = "HWREna"; @@ -9350,7 +9350,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(tcg_ctx, tcg_ctx->cpu_env, arg); ctx->base.is_jmp = DISAS_STOP;