From 3827b167e2944ce36be8a68fdaf84091f6df0fff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 3 Mar 2018 23:11:26 -0500 Subject: [PATCH] target/sparc: optimize various functions using extract op Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Backports commit 0b1183e315cce99102898bda54f69b685157a507 from qemu --- qemu/target/sparc/translate.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/qemu/target/sparc/translate.c b/qemu/target/sparc/translate.c index abc81f4b..082af557 100644 --- a/qemu/target/sparc/translate.c +++ b/qemu/target/sparc/translate.c @@ -379,8 +379,7 @@ static inline void gen_mov_reg_N(DisasContext *dc, TCGv reg, TCGv_i32 src) TCGContext *tcg_ctx = dc->uc->tcg_ctx; tcg_gen_extu_i32_tl(tcg_ctx, reg, src); - tcg_gen_shri_tl(tcg_ctx, reg, reg, PSR_NEG_SHIFT); - tcg_gen_andi_tl(tcg_ctx, reg, reg, 0x1); + tcg_gen_extract_tl(tcg_ctx, reg, reg, PSR_NEG_SHIFT, 1); } static inline void gen_mov_reg_Z(DisasContext *dc, TCGv reg, TCGv_i32 src) @@ -388,8 +387,7 @@ static inline void gen_mov_reg_Z(DisasContext *dc, TCGv reg, TCGv_i32 src) TCGContext *tcg_ctx = dc->uc->tcg_ctx; tcg_gen_extu_i32_tl(tcg_ctx, reg, src); - tcg_gen_shri_tl(tcg_ctx, reg, reg, PSR_ZERO_SHIFT); - tcg_gen_andi_tl(tcg_ctx, reg, reg, 0x1); + tcg_gen_extract_tl(tcg_ctx, reg, reg, PSR_ZERO_SHIFT, 1); } static inline void gen_mov_reg_V(DisasContext *dc, TCGv reg, TCGv_i32 src) @@ -397,8 +395,7 @@ static inline void gen_mov_reg_V(DisasContext *dc, TCGv reg, TCGv_i32 src) TCGContext *tcg_ctx = dc->uc->tcg_ctx; tcg_gen_extu_i32_tl(tcg_ctx, reg, src); - tcg_gen_shri_tl(tcg_ctx, reg, reg, PSR_OVF_SHIFT); - tcg_gen_andi_tl(tcg_ctx, reg, reg, 0x1); + tcg_gen_extract_tl(tcg_ctx, reg, reg, PSR_OVF_SHIFT, 1); } static inline void gen_mov_reg_C(DisasContext *dc, TCGv reg, TCGv_i32 src) @@ -406,8 +403,7 @@ static inline void gen_mov_reg_C(DisasContext *dc, TCGv reg, TCGv_i32 src) TCGContext *tcg_ctx = dc->uc->tcg_ctx; tcg_gen_extu_i32_tl(tcg_ctx, reg, src); - tcg_gen_shri_tl(tcg_ctx, reg, reg, PSR_CARRY_SHIFT); - tcg_gen_andi_tl(tcg_ctx, reg, reg, 0x1); + tcg_gen_extract_tl(tcg_ctx, reg, reg, PSR_CARRY_SHIFT, 1); } #if 0 @@ -682,8 +678,7 @@ static inline void gen_op_mulscc(DisasContext *dc, TCGv dst, TCGv src1, TCGv src // env->y = (b2 << 31) | (env->y >> 1); tcg_gen_andi_tl(tcg_ctx, r_temp, tcg_ctx->cpu_cc_src, 0x1); tcg_gen_shli_tl(tcg_ctx, r_temp, r_temp, 31); - tcg_gen_shri_tl(tcg_ctx, t0, tcg_ctx->cpu_y, 1); - tcg_gen_andi_tl(tcg_ctx, t0, t0, 0x7fffffff); + tcg_gen_extract_tl(tcg_ctx, t0, tcg_ctx->cpu_y, 1, 31); tcg_gen_or_tl(tcg_ctx, t0, t0, r_temp); tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_y, t0, 0xffffffff);