From 2e6d11ee477451941a0af867c7f4284dff364040 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 28 May 2019 19:17:52 -0400 Subject: [PATCH] target/riscv: Add Hypervisor CSR macros Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Backports commit 71f09a5bb48d0c51b87e70158407ec2db4a9c6e2 from qemu --- qemu/target/riscv/cpu_bits.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/qemu/target/riscv/cpu_bits.h b/qemu/target/riscv/cpu_bits.h index fe716475..3296d81b 100644 --- a/qemu/target/riscv/cpu_bits.h +++ b/qemu/target/riscv/cpu_bits.h @@ -202,6 +202,12 @@ #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 +/* Hypervisor CSRs */ +#define CSR_HSTATUS 0xa00 +#define CSR_HEDELEG 0xa02 +#define CSR_HIDELEG 0xa03 +#define CSR_HGATP 0xa80 + /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 @@ -292,9 +298,6 @@ #define CSR_MHPMCOUNTER31H 0xb9f /* Legacy Hypervisor Trap Setup (priv v1.9.1) */ -#define CSR_HSTATUS 0x200 -#define CSR_HEDELEG 0x202 -#define CSR_HIDELEG 0x203 #define CSR_HIE 0x204 #define CSR_HTVEC 0x205