From 2b2f91f82cd80dfd65e0af22449b3c48a43b4315 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Sun, 14 Jun 2020 22:28:52 -0400 Subject: [PATCH] target/riscv: Add the lowRISC Ibex CPU The reset vector is set in the init function don't set it again in realize. Backports commit 36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 from qemu --- qemu/target/riscv/cpu.c | 9 +++++++++ qemu/target/riscv/cpu.h | 1 + 2 files changed, 10 insertions(+) diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c index 7b8cff3c..94fa806f 100644 --- a/qemu/target/riscv/cpu.c +++ b/qemu/target/riscv/cpu.c @@ -136,6 +136,14 @@ static void rv32gcsu_priv1_10_0_cpu_init(struct uc_struct *uc, Object *obj, void set_feature(env, RISCV_FEATURE_PMP); } +static void rv32imcu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) +{ + CPURISCVState *env = &RISCV_CPU(uc, obj)->env; + set_misa(env, RV32 | RVI | RVM | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + set_resetvec(env, 0x8090); +} + static void rv32imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) { CPURISCVState *env = &RISCV_CPU(uc, obj)->env; @@ -377,6 +385,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h index db9bbefc..1aaff628 100644 --- a/qemu/target/riscv/cpu.h +++ b/qemu/target/riscv/cpu.h @@ -38,6 +38,7 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")