From 2a6b6c1082c8e33cd26a22ae0b365856e1d2e503 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 15 Feb 2018 11:04:41 -0500 Subject: [PATCH] target-arm: Refactor CPU affinity handling Introduces reusable definitions for CPU affinity masks/shifts and gets rid of hardcoded magic numbers. Backports commit 0f4a9e45ec35811ee250ac232d84d3c6d4fcd7fc from qemu --- qemu/target-arm/cpu-qom.h | 13 +++++++++++++ qemu/target-arm/cpu.c | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/qemu/target-arm/cpu-qom.h b/qemu/target-arm/cpu-qom.h index 96668d58..3cadc915 100644 --- a/qemu/target-arm/cpu-qom.h +++ b/qemu/target-arm/cpu-qom.h @@ -223,6 +223,19 @@ void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) + +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) + #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/qemu/target-arm/cpu.c b/qemu/target-arm/cpu.c index 9d34aa8a..f72322b6 100644 --- a/qemu/target-arm/cpu.c +++ b/qemu/target-arm/cpu.c @@ -367,7 +367,7 @@ static void arm_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque) */ Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER; Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER; - cpu->mp_affinity = (Aff1 << 8) | Aff0; + cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0; #if 0 #ifndef CONFIG_USER_ONLY