From 2a4e4446889d92663e751ede31f21f803abc549e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 4 Mar 2021 16:22:33 -0500 Subject: [PATCH] tcg/arm: Split out constraint sets to tcg-target-con-set.h Backports 7166eebb9bbe05fd956bd46b13643e1ae04c00ec --- qemu/tcg/arm/tcg-target-con-set.h | 35 +++++++++++ qemu/tcg/arm/tcg-target.h | 1 + qemu/tcg/arm/tcg-target.inc.c | 96 +++++++++++++++---------------- 3 files changed, 83 insertions(+), 49 deletions(-) create mode 100644 qemu/tcg/arm/tcg-target-con-set.h diff --git a/qemu/tcg/arm/tcg-target-con-set.h b/qemu/tcg/arm/tcg-target-con-set.h new file mode 100644 index 00000000..ab63e089 --- /dev/null +++ b/qemu/tcg/arm/tcg-target-con-set.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define Arm target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, rIN) +C_O0_I2(s, s) +C_O0_I3(s, s, s) +C_O0_I4(r, r, rI, rI) +C_O0_I4(s, s, s, s) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, l, l) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rIN) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, r, r, rI, rI) +C_O1_I4(r, r, rIN, rIK, 0) +C_O2_I1(r, r, l) +C_O2_I2(r, r, l, l) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, rIN, rIK) +C_O2_I4(r, r, rI, rI, rIN, rIK) diff --git a/qemu/tcg/arm/tcg-target.h b/qemu/tcg/arm/tcg-target.h index 3b243387..11031154 100644 --- a/qemu/tcg/arm/tcg-target.h +++ b/qemu/tcg/arm/tcg-target.h @@ -148,5 +148,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H #endif diff --git a/qemu/tcg/arm/tcg-target.inc.c b/qemu/tcg/arm/tcg-target.inc.c index 2e35ddd8..bf9ab7d0 100644 --- a/qemu/tcg/arm/tcg-target.inc.c +++ b/qemu/tcg/arm/tcg-target.inc.c @@ -2053,43 +2053,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { 0, { "r" } }; - static const TCGTargetOpDef r_r = { 0, { "r", "r" } }; - static const TCGTargetOpDef s_s = { 0, { "s", "s" } }; - static const TCGTargetOpDef r_l = { 0, { "r", "l" } }; - static const TCGTargetOpDef r_r_r = { 0, { "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l = { 0, { "r", "r", "l" } }; - static const TCGTargetOpDef r_l_l = { 0, { "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s = { 0, { "s", "s", "s" } }; - static const TCGTargetOpDef r_r_ri = { 0, { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { 0, { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rIN = { 0, { "r", "r", "rIN" } }; - static const TCGTargetOpDef r_r_rIK = { 0, { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_r_r = { 0, { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l = { 0, { "r", "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s_s = { 0, { "s", "s", "s", "s" } }; - static const TCGTargetOpDef br = { 0, { "r", "rIN" } }; - static const TCGTargetOpDef ext2 = { 0, { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef dep = { 0, { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc = { 0, { "r", "r", "rIN", "rIK", "0" } }; - static const TCGTargetOpDef add2 = { 0, { "r", "r", "r", "r", "rIN", "rIK" } }; - static const TCGTargetOpDef sub2 = { 0, { "r", "r", "rI", "rI", "rIN", "rIK" } }; - static const TCGTargetOpDef br2 = { 0, { "r", "r", "rI", "rI" } }; - static const TCGTargetOpDef setc2 = { 0, { "r", "r", "r", "rI", "rI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); + case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: case INDEX_op_bswap16_i32: @@ -2099,58 +2073,82 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ext16u_i32: case INDEX_op_extract_i32: case INDEX_op_sextract_i32: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + return C_O0_I2(r, r); + case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_setcond_i32: - return &r_r_rIN; + return C_O1_I2(r, r, rIN); + case INDEX_op_and_i32: case INDEX_op_andc_i32: case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); + case INDEX_op_mul_i32: case INDEX_op_div_i32: case INDEX_op_divu_i32: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); + case INDEX_op_or_i32: case INDEX_op_xor_i32: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: - return &r_r_ri; + return C_O1_I2(r, r, ri); + case INDEX_op_brcond_i32: - return &br; + return C_O0_I2(r, rIN); + case INDEX_op_deposit_i32: - return &dep; + return C_O1_I2(r, 0, rZ); + case INDEX_op_extract2_i32: - return &ext2; + return C_O1_I2(r, rZ, rZ); + case INDEX_op_movcond_i32: - return &movc; + return C_O1_I4(r, r, rIN, rIK, 0); + case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rIN, rIK); + case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rI, rIN, rIK); + case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, rI, rI); + case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, rI, rI); + case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l; + return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l); + case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l; + return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l); + case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s); + case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s); + default: - return NULL; + g_assert_not_reached(); } }