From 1f59a435442e832eb4fd17eb9a63464935b8b4b2 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 18 Nov 2019 23:49:30 -0500 Subject: [PATCH] Revert "target/arm: Use unallocated_encoding for aarch32" Despite the fact that the text for the call to gen_exception_insn is identical for aarch64 and aarch32, the implementation inside gen_exception_insn is totally different. This fixes exceptions raised from aarch64. This reverts commit fb2d3c9a9a9e7c3d05fc23a336698f20d525ce5b. --- qemu/arm.h | 1 - qemu/armeb.h | 1 - qemu/header_gen.py | 1 - qemu/target/arm/translate-a64.c | 7 +++++++ qemu/target/arm/translate-a64.h | 2 ++ qemu/target/arm/translate-vfp.inc.c | 3 ++- qemu/target/arm/translate.c | 22 ++++++++++------------ qemu/target/arm/translate.h | 2 -- 8 files changed, 21 insertions(+), 18 deletions(-) diff --git a/qemu/arm.h b/qemu/arm.h index e9c480c7..d4be94ce 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -3418,7 +3418,6 @@ #define sri_op sri_op_arm #define sve_exception_el sve_exception_el_arm #define sve_zcr_len_for_el sve_zcr_len_for_el_arm -#define unallocated_encoding unallocated_encoding_arm #define uqadd_op uqadd_op_arm #define uqsub_op uqsub_op_arm #define usra_op usra_op_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 834ff9cc..c309f1ad 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -3418,7 +3418,6 @@ #define sri_op sri_op_armeb #define sve_exception_el sve_exception_el_armeb #define sve_zcr_len_for_el sve_zcr_len_for_el_armeb -#define unallocated_encoding unallocated_encoding_armeb #define uqadd_op uqadd_op_armeb #define uqsub_op uqsub_op_armeb #define usra_op usra_op_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index fa7b15dd..12e0e35f 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3427,7 +3427,6 @@ arm_symbols = ( 'sri_op', 'sve_exception_el', 'sve_zcr_len_for_el', - 'unallocated_encoding', 'uqadd_op', 'uqsub_op', 'usra_op', diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 9274da64..96e46a8d 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -480,6 +480,13 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) } } +void unallocated_encoding(DisasContext *s) +{ + /* Unallocated and reserved encodings are uncategorized */ + gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); +} + static void init_tmp_a64_array(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG diff --git a/qemu/target/arm/translate-a64.h b/qemu/target/arm/translate-a64.h index 2f132fb5..fe96d76e 100644 --- a/qemu/target/arm/translate-a64.h +++ b/qemu/target/arm/translate-a64.h @@ -18,6 +18,8 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H +void unallocated_encoding(DisasContext *s); + #define unsupported_encoding(s, insn) \ do { \ qemu_log_mask(LOG_UNIMP, \ diff --git a/qemu/target/arm/translate-vfp.inc.c b/qemu/target/arm/translate-vfp.inc.c index 4b71cede..85e32679 100644 --- a/qemu/target/arm/translate-vfp.inc.c +++ b/qemu/target/arm/translate-vfp.inc.c @@ -110,7 +110,8 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); - unallocated_encoding(s); + gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); return false; } diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 89d9b162..ae72aef9 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -1304,13 +1304,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) s->base.is_jmp = DISAS_NORETURN; } -void unallocated_encoding(DisasContext *s) -{ - /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); -} - /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -1342,7 +1335,8 @@ static inline void gen_hlt(DisasContext *s, int imm) return; } - unallocated_encoding(s); + gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, @@ -7754,7 +7748,8 @@ static void gen_srs(DisasContext *s, } if (undef) { - unallocated_encoding(s); + gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); return; } @@ -9383,7 +9378,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; default: illegal_op: - unallocated_encoding(s); + gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); break; } } @@ -11070,7 +11066,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } return; illegal_op: - unallocated_encoding(s); + gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) @@ -11894,7 +11891,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) return; illegal_op: undef: - unallocated_encoding(s); + gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) diff --git a/qemu/target/arm/translate.h b/qemu/target/arm/translate.h index 8807fe65..cd1c8941 100644 --- a/qemu/target/arm/translate.h +++ b/qemu/target/arm/translate.h @@ -106,8 +106,6 @@ typedef struct DisasCompare { bool value_global; } DisasCompare; -void unallocated_encoding(DisasContext *s); - static inline int arm_dc_feature(DisasContext *dc, int feature) { return (dc->features & (1ULL << feature)) != 0;