From 1939b282762b301609e8a874b3a7f0bbda804c4b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 22 Jan 2019 16:41:15 -0500 Subject: [PATCH] target/arm: Enable PAuth for user-only Add 4 attributes that controls the EL1 enable bits, as we may not always want to turn on pointer authentication with -cpu max. However, by default they are enabled. Backports relevant parts of commit 1ae9cfbd470bffb8d9bacd761344e9b5e8adecb6 from qemu. --- qemu/target/arm/cpu.c | 3 +++ qemu/target/arm/cpu64.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 31f98123..886230b4 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -154,6 +154,9 @@ static void arm_cpu_reset(CPUState *s) env->pstate = PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; + /* Enable all PAC instructions */ + env->cp15.hcr_el2 |= HCR_API; + env->cp15.scr_el3 |= SCR_API; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c index 326fdb1a..adf14945 100644 --- a/qemu/target/arm/cpu64.c +++ b/qemu/target/arm/cpu64.c @@ -305,6 +305,10 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ + /* Enable all PAC keys by default. */ + cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB; + cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB; + cpu->sve_max_vq = ARM_MAX_VQ; }