From 15968016933ff9fed08029488076ffbfe3e5dd69 Mon Sep 17 00:00:00 2001
From: Aaron Lindsay <aclindsa@gmail.com>
Date: Tue, 23 Oct 2018 12:56:43 -0400
Subject: [PATCH] target/arm: Mask PMOVSR writes based on supported counters

This is an amendment to my earlier patch:
commit 7ece99b17e832065236c07a158dfac62619ef99b

Backports commit 599b71e277ac7e92807191b20b7163a28c5450ad from qemu
---
 qemu/target/arm/helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index 1f14f5dd..2802a572 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -1043,6 +1043,7 @@ static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
 {
+    value &= pmu_counter_mask(env);
     env->cp15.c9_pmovsr &= ~value;
 }