From 1551a961ba020d93f2739b39b2650b3cb0c0134d Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 8 Mar 2021 13:33:01 -0500 Subject: [PATCH] target/riscv: Update the CSRs to the v0.6 Hyp extension Backports 543ba53157f9003eaa9b802d44c577c5814e232c --- qemu/target/riscv/cpu_bits.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/qemu/target/riscv/cpu_bits.h b/qemu/target/riscv/cpu_bits.h index 52a536b7..aab25daf 100644 --- a/qemu/target/riscv/cpu_bits.h +++ b/qemu/target/riscv/cpu_bits.h @@ -437,16 +437,17 @@ #endif /* hstatus CSR bits */ -#define HSTATUS_SPRV 0x00000001 -#define HSTATUS_STL 0x00000040 +#define HSTATUS_VSBE 0x00000020 +#define HSTATUS_GVA 0x00000040 #define HSTATUS_SPV 0x00000080 -#define HSTATUS_SP2P 0x00000100 -#define HSTATUS_SP2V 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_VGEIN 0x0003F000 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_SPVP 0x00000100 +#if defined(TARGET_RISCV64) +#define HSTATUS_VSXL 0x300000000 +#endif #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL