From 12d33edea52565d73815780a5fdc6bdb58bab433 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 8 Mar 2021 13:33:37 -0500 Subject: [PATCH] target/riscv: Only support a single VSXL length Backports f8dc878efc45691be7e6c2019a19c271fb9aebbb --- qemu/target/riscv/csr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qemu/target/riscv/csr.c b/qemu/target/riscv/csr.c index 9757d06d..13c1e029 100644 --- a/qemu/target/riscv/csr.c +++ b/qemu/target/riscv/csr.c @@ -839,12 +839,21 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->hstatus; +#ifdef TARGET_RISCV64 + /* We only support 64-bit VSXL */ + *val = set_field(*val, HSTATUS_VSXL, 2); +#endif return 0; } static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus = val; +#ifdef TARGET_RISCV64 + if (get_field(val, HSTATUS_VSXL) != 2) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); + } +#endif return 0; }