From 12b4e01d9c0d05e54dd392d12d7d4767e5c38105 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 21 Mar 2020 16:50:51 -0400 Subject: [PATCH] tcg: Add tcg_gen_gvec_5_ptr Extend the vector generator infrastructure to handle 5 vector arguments. Backports commit 2445971604c1cfd3ec484457159f4ac300fb04d2 from qemu --- qemu/aarch64.h | 1 + qemu/aarch64eb.h | 1 + qemu/arm.h | 1 + qemu/armeb.h | 1 + qemu/header_gen.py | 1 + qemu/m68k.h | 1 + qemu/mips.h | 1 + qemu/mips64.h | 1 + qemu/mips64el.h | 1 + qemu/mipsel.h | 1 + qemu/powerpc.h | 1 + qemu/riscv32.h | 1 + qemu/riscv64.h | 1 + qemu/sparc.h | 1 + qemu/sparc64.h | 1 + qemu/tcg/tcg-op-gvec.c | 33 +++++++++++++++++++++++++++++++++ qemu/tcg/tcg-op-gvec.h | 7 +++++++ qemu/x86_64.h | 1 + 18 files changed, 56 insertions(+) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 57723e02..fa79ae91 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64 +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_aarch64 #define tcg_gen_gvec_abs tcg_gen_gvec_abs_aarch64 #define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 8ef416c6..383eb560 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64eb #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64eb #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64eb +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_aarch64eb #define tcg_gen_gvec_abs tcg_gen_gvec_abs_aarch64eb #define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64eb #define tcg_gen_gvec_addi tcg_gen_gvec_addi_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index a0b1b601..cfd2667b 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_arm #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_arm #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_arm +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_arm #define tcg_gen_gvec_abs tcg_gen_gvec_abs_arm #define tcg_gen_gvec_add tcg_gen_gvec_add_arm #define tcg_gen_gvec_addi tcg_gen_gvec_addi_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 9f6fd99c..0d1dd856 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_armeb #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_armeb #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_armeb +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_armeb #define tcg_gen_gvec_abs tcg_gen_gvec_abs_armeb #define tcg_gen_gvec_add tcg_gen_gvec_add_armeb #define tcg_gen_gvec_addi tcg_gen_gvec_addi_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 56f06b7d..58f9de8f 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -2886,6 +2886,7 @@ symbols = ( 'tcg_gen_gvec_4_ool', 'tcg_gen_gvec_4_ptr', 'tcg_gen_gvec_5_ool', + 'tcg_gen_gvec_5_ptr', 'tcg_gen_gvec_abs', 'tcg_gen_gvec_add', 'tcg_gen_gvec_addi', diff --git a/qemu/m68k.h b/qemu/m68k.h index abcc5284..c2b91f6e 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_m68k #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_m68k #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_m68k +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_m68k #define tcg_gen_gvec_abs tcg_gen_gvec_abs_m68k #define tcg_gen_gvec_add tcg_gen_gvec_add_m68k #define tcg_gen_gvec_addi tcg_gen_gvec_addi_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 12eac6d1..c340fdde 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mips #define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips #define tcg_gen_gvec_add tcg_gen_gvec_add_mips #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index dd3f4a0d..66a10f38 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64 +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mips64 #define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips64 #define tcg_gen_gvec_add tcg_gen_gvec_add_mips64 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index cb0b61e4..38e21946 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64el #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64el #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64el +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mips64el #define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips64el #define tcg_gen_gvec_add tcg_gen_gvec_add_mips64el #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 0fd78f82..b4022b1a 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mipsel #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mipsel #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mipsel +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mipsel #define tcg_gen_gvec_abs tcg_gen_gvec_abs_mipsel #define tcg_gen_gvec_add tcg_gen_gvec_add_mipsel #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index 46710795..f6c75aea 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_powerpc #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_powerpc #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_powerpc +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_powerpc #define tcg_gen_gvec_abs tcg_gen_gvec_abs_powerpc #define tcg_gen_gvec_add tcg_gen_gvec_add_powerpc #define tcg_gen_gvec_addi tcg_gen_gvec_addi_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 471f6ae0..ac1406bf 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv32 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv32 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv32 +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_riscv32 #define tcg_gen_gvec_abs tcg_gen_gvec_abs_riscv32 #define tcg_gen_gvec_add tcg_gen_gvec_add_riscv32 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index e5cbf60d..3a27e1ec 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv64 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv64 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv64 +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_riscv64 #define tcg_gen_gvec_abs tcg_gen_gvec_abs_riscv64 #define tcg_gen_gvec_add tcg_gen_gvec_add_riscv64 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv64 diff --git a/qemu/sparc.h b/qemu/sparc.h index a2206255..5dac30be 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_sparc #define tcg_gen_gvec_abs tcg_gen_gvec_abs_sparc #define tcg_gen_gvec_add tcg_gen_gvec_add_sparc #define tcg_gen_gvec_addi tcg_gen_gvec_addi_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 3ded3c10..2a24ec55 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc64 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc64 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc64 +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_sparc64 #define tcg_gen_gvec_abs tcg_gen_gvec_abs_sparc64 #define tcg_gen_gvec_add tcg_gen_gvec_add_sparc64 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_sparc64 diff --git a/qemu/tcg/tcg-op-gvec.c b/qemu/tcg/tcg-op-gvec.c index 81ca902c..95e48620 100644 --- a/qemu/tcg/tcg-op-gvec.c +++ b/qemu/tcg/tcg-op-gvec.c @@ -290,6 +290,39 @@ void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo tcg_temp_free_i32(s, desc); } +/* Generate a call to a gvec-style helper with five vector operands + and an extra pointer operand. */ +void tcg_gen_gvec_5_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_5_ptr *fn) +{ + TCGv_ptr a0, a1, a2, a3, a4; + TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data)); + + a0 = tcg_temp_new_ptr(s); + a1 = tcg_temp_new_ptr(s); + a2 = tcg_temp_new_ptr(s); + a3 = tcg_temp_new_ptr(s); + a4 = tcg_temp_new_ptr(s); + + tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs); + tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs); + tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs); + tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs); + tcg_gen_addi_ptr(s, a4, s->cpu_env, eofs); + + fn(s, a0, a1, a2, a3, a4, ptr, desc); + + tcg_temp_free_ptr(s, a0); + tcg_temp_free_ptr(s, a1); + tcg_temp_free_ptr(s, a2); + tcg_temp_free_ptr(s, a3); + tcg_temp_free_ptr(s, a4); + tcg_temp_free_i32(s, desc); +} + + /* Return true if we want to implement something of OPRSZ bytes in units of LNSZ. This limits the expansion of inline code. */ static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) diff --git a/qemu/tcg/tcg-op-gvec.h b/qemu/tcg/tcg-op-gvec.h index 8c9dbdc1..a628c08d 100644 --- a/qemu/tcg/tcg-op-gvec.h +++ b/qemu/tcg/tcg-op-gvec.h @@ -83,6 +83,13 @@ void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo uint32_t maxsz, int32_t data, gen_helper_gvec_4_ptr *fn); +typedef void gen_helper_gvec_5_ptr(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_5_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_5_ptr *fn); + /* Expand a gvec operation. Either inline or out-of-line depending on the actual vector size and the operations supported by the host. */ typedef struct { diff --git a/qemu/x86_64.h b/qemu/x86_64.h index bcbe7b06..0bfc71ca 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -2880,6 +2880,7 @@ #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_x86_64 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_x86_64 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_x86_64 +#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_x86_64 #define tcg_gen_gvec_abs tcg_gen_gvec_abs_x86_64 #define tcg_gen_gvec_add tcg_gen_gvec_add_x86_64 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_x86_64