From 10c6887e0b5459fbb8d802f6f849a794b6084769 Mon Sep 17 00:00:00 2001 From: Aaron Lindsay Date: Tue, 23 Oct 2018 12:55:57 -0400 Subject: [PATCH] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO I previously fixed this for PMINTENSET_EL1, but missed these. Backports commit fc5f6856a02168864a5c1a46866a12839322222f from qemu --- qemu/target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 965b6cbc..1f14f5dd 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -1246,9 +1246,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0}, access_tpm, NULL, pmintenset_write, NULL, raw_write }, { "PMINTENCLR", 15,9,14, 0,0,2, 0, - ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0}, + ARM_CP_ALIAS | ARM_CP_IO, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0}, access_tpm, NULL, pmintenclr_write, }, - { "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS, + { "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS | ARM_CP_IO, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0}, access_tpm, NULL, pmintenclr_write }, { "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,