From 079615b2a0aedecb13c5910af76397877c8f8458 Mon Sep 17 00:00:00 2001 From: Abdallah Bouassida Date: Sun, 20 May 2018 00:15:43 -0400 Subject: [PATCH] target/arm: Add ARM_CP_NO_GDB as a new bit field for ARMCPRegInfo type This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML. This bit is enabled automatically when creating CP_ANY wildcard aliases. This bit could be enabled manually for any register we want to remove from the dynamic XML description. Backports commit 1f16378718fa87d63f70d0797f4546a88d8e3dd7 from qemu --- qemu/target/arm/cpu.h | 3 ++- qemu/target/arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index d2bbcc9a..771e21b8 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -1787,10 +1787,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x30ff +#define ARM_CP_FLAG_MASK 0x70ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 96b838c0..f06a75e2 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -4912,7 +4912,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, if (((r->crm == CP_ANY) && crm != 0) || ((r->opc1 == CP_ANY) && opc1 != 0) || ((r->opc2 == CP_ANY) && opc2 != 0)) { - r2->type |= ARM_CP_ALIAS; + r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; } /* Check that raw accesses are either forbidden or handled. Note that