yuzu-mirror/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-mirror/unicorn.git synced 2025-12-06 07:12:03 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity
unicorn/qemu/hw/riscv/Makefile.objs

1 line
16 B
Makefile
Raw Normal View History

target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 19:06:28 +01:00
obj-y += spike.o
Reference in a new issue Copy permalink