diff --git a/include/oaknut/impl/enum.hpp b/include/oaknut/impl/enum.hpp index 89dc935..68448b4 100644 --- a/include/oaknut/impl/enum.hpp +++ b/include/oaknut/impl/enum.hpp @@ -85,15 +85,67 @@ enum class PstateField { }; enum class SystemReg { + AMCFGR_EL0 = 0b11'011'1101'0010'001, + AMCGCR_EL0 = 0b11'011'1101'0010'010, + AMCNTENCLR0_EL0 = 0b11'011'1101'0010'100, + AMCNTENCLR1_EL0 = 0b11'011'1101'0011'000, + AMCNTENSET0_EL0 = 0b11'011'1101'0010'101, + AMCNTENSET1_EL0 = 0b11'011'1101'0011'001, + AMCR_EL0 = 0b11'011'1101'0010'000, + AMEVCNTR0_n_EL0 = 0b11'011'1101'0100'000, // n = 0-3 + AMEVCNTR1_n_EL0 = 0b11'011'1101'1100'000, // n = 0-15 + AMEVTYPER0_n_EL0 = 0b11'011'1101'0110'000, // n = 0-3 + AMEVTYPER1_n_EL0 = 0b11'011'1101'1110'000, // n = 0-15 + AMUSERENR_EL0 = 0b11'011'1101'0010'011, CNTFRQ_EL0 = 0b11'011'1110'0000'000, + CNTP_CTL_EL0 = 0b11'011'1110'0010'001, + CNTP_CVAL_EL0 = 0b11'011'1110'0010'010, + CNTP_TVAL_EL0 = 0b11'011'1110'0010'000, CNTPCT_EL0 = 0b11'011'1110'0000'001, + CNTV_CTL_EL0 = 0b11'011'1110'0011'001, + CNTV_CVAL_EL0 = 0b11'011'1110'0011'010, + CNTV_TVAL_EL0 = 0b11'011'1110'0011'000, + CNTVCT_EL0 = 0b11'011'1110'0000'010, CTR_EL0 = 0b11'011'0000'0000'001, + CurrentEL = 0b11'000'0100'0010'010, + DAIF = 0b11'011'0100'0010'001, + DBGDTR_EL0 = 0b10'011'0000'0100'000, + DBGDTRRX_EL0 = 0b10'011'0000'0101'000, + DBGDTRTX_EL0 = 0b10'011'0000'0101'000, DCZID_EL0 = 0b11'011'0000'0000'111, + DIT = 0b11'011'0100'0010'101, + DLR_EL0 = 0b11'011'0100'0101'001, + DSPSR_EL0 = 0b11'011'0100'0101'000, FPCR = 0b11'011'0100'0100'000, FPSR = 0b11'011'0100'0100'001, + MDCCSR_EL0 = 0b10'011'0000'0001'000, NZCV = 0b11'011'0100'0010'000, + PAN = 0b11'000'0100'0010'011, + PMCCFILTR_EL0 = 0b11'011'1110'1111'111, + PMCCNTR_EL0 = 0b11'011'1001'1101'000, + PMCEID0_EL0 = 0b11'011'1001'1100'110, + PMCEID1_EL0 = 0b11'011'1001'1100'111, + PMCNTENCLR_EL0 = 0b11'011'1001'1100'010, + PMCNTENSET_EL0 = 0b11'011'1001'1100'001, + PMCR_EL0 = 0b11'011'1001'1100'000, + PMEVCNTR_n_EL0 = 0b11'011'1110'1000'000, // n = 0-30 + PMEVTYPER_n_EL0 = 0b11'011'1110'1100'000, // n = 0-30 + PMOVSCLR_EL0 = 0b11'011'1001'1100'011, + PMOVSSET_EL0 = 0b11'011'1001'1110'011, + PMSELR_EL0 = 0b11'011'1001'1100'101, + PMSWINC_EL0 = 0b11'011'1001'1100'100, + PMUSERENR_EL0 = 0b11'011'1001'1110'000, + PMXEVCNTR_EL0 = 0b11'011'1001'1101'010, + PMXEVTYPER_EL0 = 0b11'011'1001'1101'001, + SP_EL0 = 0b11'000'0100'0001'000, + SPSel = 0b11'000'0100'0010'000, + SPSR_abt = 0b11'100'0100'0011'001, + SPSR_fiq = 0b11'100'0100'0011'011, + SPSR_irq = 0b11'100'0100'0011'000, + SPSR_und = 0b11'100'0100'0011'010, TPIDR_EL0 = 0b11'011'1101'0000'010, TPIDRRO_EL0 = 0b11'011'1101'0000'011, + UAO = 0b11'000'0100'0010'100, }; enum class AtOp { @@ -199,7 +251,7 @@ enum class TlbiOp { VALE1 = 0b000'0111'101, VAALE1 = 0b000'0111'111, IPAS2E1IS = 0b100'0000'001, - RIPAS2E1IS = 0b100'0000'010, // ARMv8.4-TLBI + RIPAS2E1IS = 0b100'0000'010, // ARMv8.4-TLBI IPAS2LE1IS = 0b100'0000'101, RIPAS2LE1IS = 0b100'0000'110, // ARMv8.4-TLBI ALLE2OS = 0b100'0001'000, // ARMv8.4-TLBI @@ -214,11 +266,11 @@ enum class TlbiOp { ALLE1IS = 0b100'0011'100, VALE2IS = 0b100'0011'101, VMALLS12E1IS = 0b100'0011'110, - IPAS2E1OS = 0b100'0100'000, // ARMv8.4-TLBI + IPAS2E1OS = 0b100'0100'000, // ARMv8.4-TLBI IPAS2E1 = 0b100'0100'001, - RIPAS2E1 = 0b100'0100'010, // ARMv8.4-TLBI - RIPAS2E1OS = 0b100'0100'011, // ARMv8.4-TLBI - IPAS2LE1OS = 0b100'0100'100, // ARMv8.4-TLBI + RIPAS2E1 = 0b100'0100'010, // ARMv8.4-TLBI + RIPAS2E1OS = 0b100'0100'011, // ARMv8.4-TLBI + IPAS2LE1OS = 0b100'0100'100, // ARMv8.4-TLBI IPAS2LE1 = 0b100'0100'101, RIPAS2LE1 = 0b100'0100'110, // ARMv8.4-TLBI RIPAS2LE1OS = 0b100'0100'111, // ARMv8.4-TLBI