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8 commits

Author SHA1 Message Date
Lioncash fab3a59e05 A32: Implement ARM-mode BFC 2020-04-22 21:02:46 +01:00
Lioncash 7305d13221 A32: Implement ARM-mode RBIT 2020-04-22 21:02:46 +01:00
Lioncash b2f7a0e7ba A32: Implement ARM-mode SDIV/UDIV 
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
 2020-04-22 21:02:46 +01:00
V.Kalyuzhny 764a93bf5a Switch boost::optional to std::optional 2020-04-22 20:57:37 +01:00
MerryMage f73104633b a32_emit_x64: Fix incorrect BMI2 implementation for SetCpsr 
* The MSB for each byte in cpsr_ge were not being appropriately set.
* We also expand test coverage to test this case.
* We fix the disassembly of the MSR (imm) and MSR (reg) instructions as well.
 2020-04-22 20:53:46 +01:00
Lioncash b38dd191bd disassembler_arm: Remove rotation helper function in favor of Common::RotateRight 
Mildly reduces the amount of duplicated behavior
 2020-04-22 20:46:17 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage b3c73e2622 Label A32 specific code appropriately 2020-04-22 20:33:30 +01:00
Renamed from src/frontend/disassembler/disassembler_arm.cpp (Browse further)