Commit graph

97 commits

Author SHA1 Message Date
MerryMage 795b9bea9a Remove ChangeProcessorID hack
* No library users require this hack any longer.
2021-05-01 20:33:14 +01:00
MerryMage c788bcdf17 block_of_code: Enable configuration of code cache sizes 2021-04-02 11:17:46 +01:00
Lioncash c66afadbc1 thumb32: Implement PLI variants 2021-03-06 09:55:29 -05:00
rufi 77621a8448 implemented other ic instructions 2021-02-17 20:38:08 +00:00
emuplz 8728444af8 added support for instruction ic ivau 2021-02-17 20:38:06 +00:00
MerryMage 7e5ae6076a A32: Add arch_version option 2021-02-07 12:13:14 +00:00
bunnei de389968eb A32: Add hook_isb option. 2021-01-28 20:47:39 -08:00
MerryMage 0f27368fda A64: Add hook_isb option 2021-01-26 23:41:21 +00:00
MerryMage eeeafaf5fb Introduce Unsafe_InaccurateNaN 2021-01-01 07:18:05 +00:00
ReinUsesLisp 4a9a0d07f7 backend/{a32,a64}_emit_x64: Add config entry to mask page table pointers
Add config entry to mask out the lower bits in page table pointers.
This is intended to allow users of Dynarmic to pack small integers
inside pointers and update the pair atomically without locks.
These lower bits can be masked out due to the expected alignment in
pointers inside the page table.

For the given usage, using AND on the pointer acts the same way as a
TEST instruction. That said when the mask value is zero, TEST is still
emitted to keep the same behavior.
2020-12-29 19:16:46 +00:00
MerryMage d05d95c132 Improve documentation of unsafe optimizations 2020-07-12 12:41:11 +01:00
MerryMage 761e95eec0 A64: Add unsafe_optimizations option
* Strength reduce FMA unsafely
2020-07-06 21:02:30 +01:00
MerryMage 82868034d3 A32/ASIMD: Ensure decoder table is correct
* Raise a DecoderError instead of ASSERT-ing on a decode error
* Correct ASIMD decode table
* Write a test which verifies every possible ASIMD instruction
2020-07-05 18:45:42 +01:00
MerryMage 4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage 46445d0866 A64: Remove NaN accuracy setting
Always do accuracte NaN handling.
2020-06-24 22:26:10 +01:00
Fernando Sahmkow 2fa1c1d13c A32: Allow cleaning up exclusive state from the interface.
This function is normally required for emulating certain OS mechanisms.
2020-06-21 18:18:33 +01:00
MerryMage b88c291f81 A32: Detect misaligned memory accesses
This avoids issues with misaligned memory accesses writing into the next page.
2020-06-17 17:51:37 +01:00
MerryMage 9f3277540a Merge A32 and A64 exclusive monitors 2020-06-17 10:33:09 +01:00
MerryMage a1c9bb94a8 A32: Add yuzu-specific hacks 2020-06-16 17:54:21 +01:00
MerryMage 2c1a4843ad A32 global exlcusive monitor 2020-06-16 17:54:21 +01:00
MerryMage 62e04845b1 A64/config: Provide default implementation of MemoryWriteExclusive functions
Returning false is always safe, because this means the exclusive write has failed.
2020-06-16 13:00:37 +01:00
MerryMage 2796a85096 interface/a32: Remove descriptor argument from Disassemble 2020-06-12 15:27:42 +01:00
Fernando Sahmkow d7abae1e31 A64: Implement Exceptional Exit. 2020-05-03 01:40:37 +01:00
Fernando Sahmkow 41521ed856 User Config: Add option to specify wall clock CNTPCT. 2020-05-03 01:40:37 +01:00
Fernando Sahmkow 97b9d3e058 Exclusive Monitor: Rework exclusive monitor interface. 2020-05-03 01:40:37 +01:00
Fernando Sahmkow b5d8b24a3c Exclusive Monitor: Allow clearing a single processor. 2020-05-03 01:40:36 +01:00
Fernando Sahmkow 2068658a82 A64 Interface: Allow changing processor id.
This commit allows the JIT to be used per guest thread and change it's
core when the thread is migrated.
2020-05-03 01:40:36 +01:00
MerryMage 94d0d33e02 Fix single stepping for certain instructions
Several issues:
1. Several terminal instructions did not stop at the end of a single-step block
2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag

We also introduce the enable_optimizations parameter to the A32 frontend.
2020-04-24 11:44:38 +01:00
MerryMage a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage 0c51313479 A64: Add enable_optimizations configuration option
Allow library users to disable optimizations for debugging reasons.
2020-04-22 21:06:18 +01:00
MerryMage 4636055646 a32_emit_x64: Implement fastmem 2020-04-22 21:06:17 +01:00
MerryMage b6536115ef A32: Add Step 2020-04-22 21:06:17 +01:00
MerryMage f69c77391e A64: Add Step
Allow for stepping instruction-by-instruction
2020-04-22 21:06:17 +01:00
MerryMage 5d93e6e580 print_info: Add -exec parameter to test execution 2020-04-22 21:04:24 +01:00
MerryMage a59c335b05 A64: Add options for detecting misaligned loads and stores 2020-04-22 21:04:23 +01:00
Marshall Mohror 1ebc1895ee A32/x64: Create a global_offset optimization for the page table (#507)
Instead of looking up the page table like:
  table[addr >> 12][addr & 0xFFF]
We can use a global offset on the table to query the memory like:
  table[addr >> 12][addr]

This saves two instructions on *every* memory access within the recompiler.

Original change by degasus in A64 emitter
2020-04-22 21:04:23 +01:00
Markus Wick 93668c24be A64/x64: Create a global_offset optimization for the page table.
Instead of looking up the page table like:
  table[addr >> 12][addr & 0xFFF]
We can use a global offset on the table to query the memory like:
  table[addr >> 12][addr]

This saves two instructions on *every* memory access within the recompiler.

Thanks at skmp for the idea.
2020-04-22 21:04:23 +01:00
MerryMage c7d20f3f2f fuzz_arm: Test MSR and MRS instructions against unicorn
* Add always_little_endian option to mach unicorn behavior.
* Correct CPSR.Mode = Usermode
2020-04-22 21:04:23 +01:00
MerryMage 717bd2fbb2 A64: Add hook_hint_instructions option 2020-04-22 21:04:23 +01:00
MerryMage 396116ee61 A32: Add hook_hint_instructions option 2020-04-22 21:04:23 +01:00
Lioncash 6b9bf7868a General: Correct typos is code comments 2020-04-22 21:04:22 +01:00
Lioncash 25750ad2a2 A32/coprocessor: Remove lingering boost mention in documentation comment
This should have been changed to mention std::monostate, but was
overlooked during the transition to standardized facilities.
2020-04-22 21:04:22 +01:00
Merry f6f0b6da65 Merge pull request #497 from lioncash/boost
A32/coprocessor: Remove boost from public interface
2020-04-22 21:02:47 +01:00
Lioncash 92daae9513 A32/coprocessor: Remove boost from public interface
Removes a boost header from the public includes in favor of using the
standard-provided std::variant.

The use of boost in public interfaces is often a dealbreaker for some
people. Given we use std::optional in the header already, we can
transition over to std::variant from boost::variant.

With this removal, this makes all of our dependencies internal to the
library itself.
2020-04-22 21:02:47 +01:00
Lioncash 9a097e307f A32: Implement the ARM-mode variant of SEVL 2020-04-22 21:02:47 +01:00
Lioncash 0fa0bca22a A32: Handle different variants of PLD 2020-04-22 21:02:47 +01:00
Lioncash 966e04d03d A32: Allow hooking of hint instructions in ARM mode.
Mirrors the hooking functionality from the AArch64 frontend to make the
behavior of both consistent.
2020-04-22 21:02:46 +01:00
Lioncash 2e180a7f14 backend/x64/a32_interface: Mark Context move constructor and move assignment as noexcept
Provides a more "correct" move constructor/assignment operator, since
these relevant functions shouldn't throw exceptions.

Has the benefit of playing nicely with std::move_if_noexcept and other
noexcept library facilities.
2020-04-22 20:58:09 +01:00
V.Kalyuzhny 764a93bf5a Switch boost::optional to std::optional 2020-04-22 20:57:37 +01:00
Lioncash 6b5ea6ee66 A64: Implement BRK
Currently, we can just implement this as part of the exception
interface, similar to how it's done for the A32 interface with BKPT.
2020-04-22 20:55:06 +01:00