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89 commits

Author SHA1 Message Date
MerryMage e9e7ac6e65 decoder/arm: Correct PLD decoder for v6K 2016-08-18 18:19:34 +01:00
Lioncash 9ed9f4c565 mp: Generalize function information retrieval 
Generalizes MemFnInfo to be compatible with all function types.
Also adds type introspection for arguments, as well as helper templates for the common types supported by all partial specializations.
 2016-08-17 10:08:40 +01:00
MerryMage e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
bunnei 30f3d869cc TranslateArm: Implement VPUSH and VPOP. 2016-08-13 19:37:03 +01:00
MerryMage 1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
bunnei 8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage d0d51ba346 TranslateArm: Implement STM, STMDA, STMDB, STMIB 2016-08-08 22:49:11 +01:00
MerryMage 85549d7ae2 TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB 2016-08-08 22:26:06 +01:00
MerryMage 3a465ba4a8 VFP: Implement VLDR 2016-08-07 19:59:35 +01:00
MerryMage a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage 0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage cd8e7c0504 VFP: Implement VNEG 2016-08-07 12:04:21 +01:00
MerryMage da33af5abe VFP: Implement VMLA, VMLS, VNMLA, VNMLS 2016-08-07 11:49:06 +01:00
MerryMage 3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage 12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage 97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage 4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage 8ff414ee0e Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top. 2016-08-06 20:03:15 +01:00
bunnei 8c2300d477 arm: Implement LDRD reg/imm instructions. 2016-08-05 20:05:02 -04:00
bunnei ec3a98cf95 arm: Implement LDRH reg/imm instructions. 2016-08-05 20:05:01 -04:00
bunnei 192a0fba7a arm: Implement LDRB reg/imm instructions. 2016-08-05 20:05:00 -04:00
bunnei dfb318f208 arm: Implement STRD reg/imm instructions. 2016-08-05 20:04:59 -04:00
bunnei e931dc2496 arm: Implement STRH reg/imm instructions. 2016-08-05 20:04:58 -04:00
bunnei 9f77662b24 arm: Implement STRB reg/imm instructions. 2016-08-05 20:04:57 -04:00
bunnei caab1bbc7c arm: Implement STR reg/imm instructions. 2016-08-05 20:04:56 -04:00
bunnei b09ecb4532 arm: Implement LDR reg/imm instructions. 2016-08-05 20:04:55 -04:00
Tillmann Karras eb2e6e8bea Implement some multiplies 2016-08-05 02:09:54 +01:00
bunnei 691e4139fa arm: Implement B/BL/BX instructions. 2016-08-03 16:49:01 -04:00
Tillmann Karras fc33f1d374 Implement more instructions 
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
 2016-08-03 00:47:17 +01:00
Tillmann Karras 30a90295b9 Implement data processing instructions 
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST

The code could use some serious deduplication...
 2016-08-03 00:47:16 +01:00
MerryMage 90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage 98bd7ff6a5 Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support. 2016-07-20 12:08:17 +01:00
Merry 95316b8443 Merged in Subv/dynarmic/arm_mem_tests (pull request #4) 
Added some fuzz tests for most cases of ARM Load/Store instructions
 2016-07-20 10:19:55 +01:00
MerryMage 3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
MerryMage e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
Subv ccc61472b9 Added format strings for ARM STRBT encodings A1 and A2 2016-07-18 14:20:58 -05:00
Subv 8617bf80a1 Added format strings for ARM LDRBT encodings A1 and A2 2016-07-18 14:18:39 -05:00
Subv 5d5ea9325c Added format strings for ARM STRT encodings A1 and A2 2016-07-18 14:05:53 -05:00
MerryMage 2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. 2016-07-18 20:05:35 +01:00
Subv 77761ba032 Added the format strings for LDRT encodings A1 and A2. 2016-07-18 14:01:18 -05:00
MerryMage 14dcb18bbe Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2) 2016-07-18 18:48:08 +01:00
MerryMage a605a43ef9 Implement Thumb Instructions: STRH (imm), LDRH (imm) 2016-07-18 18:28:52 +01:00
MerryMage f9755870bb Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg) 2016-07-18 18:02:02 +01:00
MerryMage dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
MerryMage f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage 9109b226af Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm) 2016-07-18 11:16:12 +01:00
MerryMage c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage bf99ddd065 Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic 2016-07-18 10:33:52 +01:00