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869 commits

Author SHA1 Message Date
Lioncash e8b0f25dff A64: Implement SQSHL's vector register variant 2020-04-22 20:55:06 +01:00
Lioncash b14eaaec46 ir: Add opcodes for left signed saturated shifts 2020-04-22 20:55:06 +01:00
Lioncash da55ed7b31 branch: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash 867b666285 move_wide: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash 78024a9dc4 load_store_register_unprivileged: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash e45e5da610 load_store_register_immediate: Place conditional bodies on their own line 
Makes the conditionals visually consistent with the rest of the
codebase.
 2020-04-22 20:55:06 +01:00
Lioncash b586cf3f56 load_store_load_literal: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash c3a3b9687e data_processing_logical: Move datasize declarations after early-exit conditionals 
While we're at it, make variables const where applicable.
 2020-04-22 20:55:06 +01:00
Lioncash ed797e6540 data_processing_conditional_select: Make variables const where applicable 
Makes CSEL's function consistent with all of the others.
 2020-04-22 20:55:06 +01:00
Lioncash c82fa5ec5a data_processing_addsub: Move datasize declarations after early-exit conditionals 
While we're at it, also make relevant variables const where applicable
 2020-04-22 20:55:06 +01:00
Lioncash f4a66d2477 data_processing_bitfield: Move datasize variables after early-exit conditionals 
Moves the declaration of datasize to the scope that it's used within.
This also takes the opportunity to apply const where applicable, and
make early-exits all vertically consistent with one another.
 2020-04-22 20:55:06 +01:00
Lioncash 2e0fcd6161 A64: Implement CLS's vector variant 
Leverages CLZ like the integral variant does.
 2020-04-22 20:55:06 +01:00
MerryMage 12243692f5 A64: Implement SQRDMULH (vector), vector variant 2020-04-22 20:55:06 +01:00
MerryMage a9ffcf08b1 A64: Implement SQDMULL (vector), vector variant 2020-04-22 20:55:06 +01:00
MerryMage 3e447614c6 IR: Add VectorSignedSaturatedDoublingMultiplyLong 2020-04-22 20:55:06 +01:00
MerryMage 06b31448aa emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply 
* Return both the upper and lower parts of the multiply if required
* SSE2 does not support the pmuldq instruction, do sign correction to an unsigned result instead
* Improve port utilisation where possible (punpck instructions were a bottleneck)
 2020-04-22 20:55:06 +01:00
MerryMage 08c0e017a5 IR: Implement Vector{Signed,Unsigned}Multiply{16,32} 2020-04-22 20:55:06 +01:00
Lioncash 112cff9ab9 A64: Implement CLZ's vector variant 2020-04-22 20:55:06 +01:00
Lioncash e739624296 ir: Add opcodes for vector CLZ operations 
We can optimize these cases further for with the use of a fair bit of
shuffling via pshufb and the use of masks, but given the uncommon use of
this instruction, I wouldn't consider it to be beneficial in terms of
amount of code to be worth it over a simple manageable naive solution
like this.

If we ever do hit a case where vectorized CLZ happens to be a
bottleneck, then we can revisit this. At least with AVX-512CD, this can
be done with a single instruction for the 32-bit word case.
 2020-04-22 20:55:05 +01:00
MerryMage d4c37a68a8 A64/translate: VectorZeroUpper for V(64) stores 
Ensures correctness.
 2020-04-22 20:55:05 +01:00
MerryMage b8daa4feac simd_two_register_misc: FNEG (vector) with Q == 0 had dirty upper 2020-04-22 20:55:05 +01:00
Lioncash 14e026a7f0 A64: Implement USQADD's scalar and vector variants 2020-04-22 20:55:05 +01:00
Lioncash d4a76aaa04 ir: Add opcodes form unsigned saturated accumulations of signed values 2020-04-22 20:55:05 +01:00
Lioncash 18ad7f237d A64: Implement SUQADD's scalar and vector variants 2020-04-22 20:55:05 +01:00
Lioncash 6f911a26da ir: Add opcodes for signed saturated accumulations of unsigned values 2020-04-22 20:55:05 +01:00
Lioncash 9a3d38d2ee A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants 
We can simply modify the general function made for SMULL{2} and
UMULL{2}'s by-element variants to also handle the other multiply-based
by-element variants.
 2020-04-22 20:55:05 +01:00
Lioncash 6ccfbc9b39 A64: Implement UMULL{2}'s vector by-element variant 2020-04-22 20:55:05 +01:00
Lioncash 58e21f175c A64: Implement SMULL{2}'s vector by-element variant 2020-04-22 20:55:05 +01:00
Lioncash 134bb02e19 ir/value: Replace includes with forward declarations 
enum classes are still considered complete types when forward declared
(as the compiler knows the exact size of the type from the declaration
alone). The only difference in this case being that the members of the
enum class aren't visible. Given we don't use the members within this
header in any way, we can simply forward declare them here and remove
the inclusions.
 2020-04-22 20:55:05 +01:00
Lioncash 2c8e07e7d0 ir/cond: Migrate to C++17 nested namespace specifiers 2020-04-22 20:55:05 +01:00
Lioncash 0a3976059f A64: Implement URSQRTE 2020-04-22 20:55:05 +01:00
Lioncash b6e74fd17d ir: Add opcodes for performing unsigned reciprocal square root estimates 2020-04-22 20:55:05 +01:00
Lioncash bd3582e811 A64: Implement URECPE 2020-04-22 20:55:05 +01:00
Lioncash af83360f89 ir: Add opcodes for unsigned reciprocal estimate 2020-04-22 20:55:05 +01:00
Lioncash 740ffa52ae A64: Implement SQNEG's scalar and vector variant 2020-04-22 20:53:46 +01:00
Lioncash fca7eddb9e A64: Add opcodes for signed saturating negations 2020-04-22 20:53:46 +01:00
Lioncash f5fb496e7e A64: Implement SQDMULH's by-element scalar variant 2020-04-22 20:53:46 +01:00
Lioncash 40f0576995 A64: Implement SQDMULH's by-element vector variant 2020-04-22 20:53:46 +01:00
MerryMage 9b65100660 A64: Implement FastDispatchHint 2020-04-22 20:53:46 +01:00
MerryMage f96c43d422 A32: Implement FastDispatchHint 2020-04-22 20:53:46 +01:00
MerryMage aa8d826c13 ir/terminal: Add FastDispatchHint 2020-04-22 20:53:46 +01:00
Lioncash 1a69a61cb4 A64: Implement SQDMULH's scalar variant 2020-04-22 20:53:46 +01:00
Lioncash 7ebfd0f31c ir: Add opcodes for scalar signed saturated doubling multiplies 2020-04-22 20:53:46 +01:00
Lioncash 9c03311fed A64: Implement SQDMULH's vector variant 2020-04-22 20:53:46 +01:00
Lioncash a0231e5546 ir: Add opcodes for signed saturated doubling multiplies 2020-04-22 20:53:46 +01:00
Lioncash db24e1f09b A64: Implement SQABS' scalar variant 2020-04-22 20:53:46 +01:00
Lioncash bda5d14c7f A64: Implement SQABS' vector variant. 2020-04-22 20:53:46 +01:00
Lioncash 0507e47420 ir: Add opcodes for signed saturated absolute values 2020-04-22 20:53:46 +01:00
MerryMage 3415828fb4 IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64} 2020-04-22 20:53:46 +01:00
Lioncash e30f9816ec A32/decoder: Add missing <algorithm> includes 
These includes should be present, as we use std::find_if() within these headers.
 2020-04-22 20:53:46 +01:00