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40 commits

Author SHA1 Message Date
Mat M a465b2ddbc ir_emitter: Fix typo. ClearExlcusive -> ClearExclusive (#5) 2016-09-02 12:17:22 +01:00
MerryMage dca3b2f079 Implement VMRS and VMSR 2016-08-26 22:47:54 +01:00
MerryMage 30df51c2dc ir_emitter: Should be in the IR namespace, not the Arm namespace 2016-08-25 17:36:42 +01:00
Lioncash 0e12fb6a56 basic_block: Move all variables behind a public interface 2016-08-25 16:14:37 +01:00
MerryMage b5a86889cd Implement VCVT 2016-08-23 22:20:04 +01:00
Lioncash 23d190f7b0 intrusive_list: Support inserters 
Allows std::inserter, std::back_inserter, and std::front_inserter to work
with intrusive lists.
 2016-08-19 20:25:17 +01:00
MerryMage e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
MerryMage 960d14d18e Optimization: Implement Return Stack Buffer 2016-08-13 00:10:23 +01:00
bunnei 8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei 4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei 127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei 86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage 2eec43178a IR: Opaque can be of any type 2016-08-09 22:46:44 +01:00
Tillmann Karras 5d26899ac9 Add simplified LogicalShiftRight64 IR opcode 2016-08-08 22:27:05 +01:00
Tillmann Karras ccb2aa96a5 Add support for the APSR.Q flag 2016-08-08 22:27:04 +01:00
MerryMage a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage 0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage 3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage 12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage 97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage 94b99f5949 Common: Add an intrusive list implementation; remove use of boost::intrusive::list. 2016-08-06 22:23:01 +01:00
Tillmann Karras 846d07d7b5 Add Sub64 opcode 2016-08-06 21:17:11 +01:00
Tillmann Karras b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
Tillmann Karras 01aebcb385 Remove *MulHi wrappers 2016-08-06 21:17:11 +01:00
MerryMage 4d127c19dd Common: Add a memory pool implementation, remove use of boost::pool 2016-08-06 20:41:00 +01:00
MerryMage 4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage 640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} 2016-08-05 19:06:10 +01:00
MerryMage b4aa01ccf4 Merge remote-tracking branch 'tilkax/master' 2016-08-05 14:14:06 +01:00
MerryMage ca40015145 IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint) 2016-08-05 14:07:27 +01:00
Tillmann Karras 3fdc093d10 Add more IR opcodes for multiply instructions 
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
 2016-08-05 02:09:30 +01:00
Tillmann Karras 2488926341 Add IR opcode RotateRightExtended 
to rotate through the carry flag
 2016-08-03 00:47:16 +01:00
MerryMage 93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage 51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage 90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
MerryMage f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage 3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage 07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
Renamed from src/frontend/ir_emitter.cpp (Browse further)