Commit graph

73 commits

Author SHA1 Message Date
Lioncash e2bc7eeb93 thumb32: Implement REVSH 2021-02-01 15:16:53 -05:00
Lioncash 95dabcf48e fuzz_thumb: Allow running only Thumb-16 tests 2021-02-01 15:04:29 -05:00
Lioncash 1ad99bb9b5 thumb32: Implement SEL 2021-02-01 15:01:21 -05:00
Lioncash 8d53048750 thumb32: Implement CLZ
Also fleshes out the generator to allow for generating thumb32
instructions as well.
2021-02-01 14:54:04 -05:00
MerryMage 4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage 3eed024caf asimd_three_same: Ignore Q=1 for VPADD (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage 2008fda88b emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed 2020-06-22 22:54:38 +01:00
MerryMage 3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) 2020-06-22 22:08:58 +01:00
MerryMage 69a1d58a2b A32: Implement ASIMD VMULL 2020-06-21 10:00:24 +01:00
MerryMage 70d071e6ab fuzz_arm: Test large random blocks 2020-06-21 00:41:54 +01:00
MerryMage 214c1d6002 fuzz_arm: Test testable parts of ASIMD VRECPE and VRSQRTE 2020-06-20 15:17:39 +01:00
MerryMage 92cb4a5a34 A32: Implement ASIMD VRSQRTE 2020-06-20 15:13:22 +01:00
MerryMage 8912496206 fuzz_arm: Unicorn has incorrect VRSQRTS implementation 2020-06-20 15:07:50 +01:00
MerryMage 6f59c2cd8e A32: Implement ASIMD VRECPE 2020-06-20 15:07:06 +01:00
MerryMage d3dc50d718 A32: Implement ASIMD VRSQRTS 2020-06-20 15:06:06 +01:00
MerryMage f58e247ef3 A32: Implement ASIMD VPADD (floating-point) 2020-06-20 14:25:04 +01:00
Lioncash ed6ca58058 A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.

In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-20 00:50:40 +01:00
MerryMage 7402d38675 test_arm_instructions: Add vclt.f32 (zero) test 2020-06-18 17:59:44 +01:00
Lioncash 9b06a938a9 fuzz_arm: Ignore endian bit
A recent change from Qemu (268b1b3dfbb92a9348406f728a33f39e3d8dcd8)
allows user space modification of the E bit.
2020-06-16 01:53:21 +01:00
MerryMage 2796a85096 interface/a32: Remove descriptor argument from Disassemble 2020-06-12 15:27:42 +01:00
MerryMage e953f67201 emit_x64_packed: PackedAbsDiffSumS8: Fix case when bits above the lower 32 bits are not zero 2020-06-12 15:24:09 +01:00
MerryMage 1a0bc5ba91 A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple) 2020-05-16 14:11:23 +01:00
MerryMage e7f1a0d408 A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H} 2020-05-15 21:07:36 +01:00
MerryMage 7f77a04900 fuzz_arm: Do not test vfp_VMRS
This may emit a vmrs *, fpscr instruction.
This results in fuzz failures due to slight inaccuracies in fpscr emulation.
2020-05-10 14:47:21 +01:00
MerryMage 6df660c889 fuzz_arm: Ensure all instructions are fuzzed
* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
2020-05-10 13:57:39 +01:00
MerryMage 94d0d33e02 Fix single stepping for certain instructions
Several issues:
1. Several terminal instructions did not stop at the end of a single-step block
2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag

We also introduce the enable_optimizations parameter to the A32 frontend.
2020-04-24 11:44:38 +01:00
MerryMage a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage 668a43f815 A32: Detect unpredictable LDM/STM instructions 2020-04-22 21:06:18 +01:00
MerryMage cb971d3280 test_arm_instruction: Revive some old tests 2020-04-22 21:04:23 +01:00
MerryMage 39bd2c034d constant_propagation_pass: Handle GetCarryFromOp for MostSignificantWord 2020-04-22 21:04:23 +01:00
MerryMage 1aa7b62e92 A32/Thumb: Correct behaviour for UDF and Unpredictable instructions
Raise an exception instead of calling the interpreter and ASSERT-ing respectively.
2020-04-22 21:04:23 +01:00
MerryMage c7d20f3f2f fuzz_arm: Test MSR and MRS instructions against unicorn
* Add always_little_endian option to mach unicorn behavior.
* Correct CPSR.Mode = Usermode
2020-04-22 21:04:23 +01:00
Merry fd6222f0a1 Merge pull request #500 from lioncash/cbz
A32: Implement Thumb-1's CBZ/CBNZ instructions
2020-04-22 21:04:21 +01:00
MerryMage 0495b2c779 tests: Fix Windows build when DYNARMIC_TESTS_USE_UNICORN is enabled 2020-04-22 21:04:21 +01:00
Lioncash 03e6899fd7 A32: Implement Thumb-1's CBZ/CBNZ instructions
Introduced in ARMv6T2, this allows for short forward branches.
2020-04-22 21:02:47 +01:00
Lioncash 0fa0bca22a A32: Handle different variants of PLD 2020-04-22 21:02:47 +01:00
MerryMage 99b284b1b5 fuzz_thumb: Disable fuzzing longer blocks 2020-04-22 21:02:47 +01:00
Lioncash 97277c598b A32: Rename vfp2-related files to vfp
Now that we fuzz against Unicorn, we aren't just restricted to VFPv2.
VFPv3 and VFPv4 facilities can now be implemented. This renames
constructs mentioning VFPv2 to just refer to VFP.
2020-04-22 21:02:46 +01:00
Lioncash 0b15fc9755 a32/fuzz_arm: Use same fuzzing mechanism as AArch64
Introduces the same fuzzing mechanism used by the AArch64 code for
fuzzing instruction implementations, getting rid of the need to
manually specify the instruction generator sequences--replacing it with
an instruction blacklist instead.

Much of this change originates from a previous patch made by Mary. This
just makes it interact nicely with the alterations made to get Unicorn
to cooperate properly.
2020-04-22 21:02:46 +01:00
Lioncash 7fc3bd689d A32: Implement ARM-mode MLS 2020-04-22 21:02:46 +01:00
Lioncash 8b338b7def A32: Implement ARM-mode MOVT 2020-04-22 21:02:46 +01:00
Lioncash 877fa0f8c3 A32: Implement ARM-mode SBFX 2020-04-22 21:02:46 +01:00
Lioncash 47218ee65d A32: Implement ARM-mode UBFX 2020-04-22 21:02:46 +01:00
Lioncash 2970b34e3c A32: Implement ARM-mode BFI 2020-04-22 21:02:46 +01:00
Lioncash fab3a59e05 A32: Implement ARM-mode BFC 2020-04-22 21:02:46 +01:00
Lioncash 7305d13221 A32: Implement ARM-mode RBIT 2020-04-22 21:02:46 +01:00
Lioncash b2f7a0e7ba A32: Implement ARM-mode SDIV/UDIV
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
2020-04-22 21:02:46 +01:00
Lioncash 57be160524 fuzz_arm: Tidy up existing tests
Now that we utilize C++17, we can use std::array's deduction guides to
avoid the need to explicitly specify the template arguments.

While we're at it, also use const where applicable.
2020-04-22 21:02:46 +01:00
Lioncash 4f2b60c8e7 dynarmic_tests: Remove skyeye interpreter
This is quite a messy interpreter and would require a large amount of
work to bring it up to speed to begin implementing newer portions of the
AArch32 instruction set into Dynarmic.

Given we already have fuzzing with Unicorn set up for
AArch64/AArch32, we can get rid of this and unify our testing
infrastructure.

This will also make building the tests much faster, given a whole
interpreter doesn't need to be built anymore as part of the project.
2020-04-22 21:02:45 +01:00
Lioncash d29582a0e1 A32: Fuzz instructions using unicorn
While skyeye was OK previously, now that we have an AArch64 backend,
this also means that we eventually have to support the AArch32
counterpart to it. Unfortunately, SkyEye is only compatible up to
ARMv6K, so we woud need to do a lot of work to bring the interpreter up
to speed with things to even begin testing new instruction
implementations.

For the AArch64 side of things, we already use Unicorn, so we can toss
out SkyEye in favor of it instead.
2020-04-22 21:02:45 +01:00