Commit graph

326 commits

Author SHA1 Message Date
Lioncash e2bc7eeb93 thumb32: Implement REVSH 2021-02-01 15:16:53 -05:00
Lioncash 95dabcf48e fuzz_thumb: Allow running only Thumb-16 tests 2021-02-01 15:04:29 -05:00
Lioncash 1ad99bb9b5 thumb32: Implement SEL 2021-02-01 15:01:21 -05:00
Lioncash 8d53048750 thumb32: Implement CLZ
Also fleshes out the generator to allow for generating thumb32
instructions as well.
2021-02-01 14:54:04 -05:00
MerryMage 80adb289d0 print_info: Use std::nullopt instead of {} 2020-09-22 18:40:00 +01:00
MerryMage 82868034d3 A32/ASIMD: Ensure decoder table is correct
* Raise a DecoderError instead of ASSERT-ing on a decode error
* Correct ASIMD decode table
* Write a test which verifies every possible ASIMD instruction
2020-07-05 18:45:42 +01:00
MerryMage 4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage 3eed024caf asimd_three_same: Ignore Q=1 for VPADD (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage 2008fda88b emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed 2020-06-22 22:54:38 +01:00
MerryMage 3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) 2020-06-22 22:08:58 +01:00
MerryMage fa145ae401 a32_unicorn: Print code on unicorn error 2020-06-21 16:23:01 +01:00
MerryMage 69a1d58a2b A32: Implement ASIMD VMULL 2020-06-21 10:00:24 +01:00
MerryMage 70d071e6ab fuzz_arm: Test large random blocks 2020-06-21 00:41:54 +01:00
MerryMage 214c1d6002 fuzz_arm: Test testable parts of ASIMD VRECPE and VRSQRTE 2020-06-20 15:17:39 +01:00
MerryMage 92cb4a5a34 A32: Implement ASIMD VRSQRTE 2020-06-20 15:13:22 +01:00
MerryMage 8912496206 fuzz_arm: Unicorn has incorrect VRSQRTS implementation 2020-06-20 15:07:50 +01:00
MerryMage 6f59c2cd8e A32: Implement ASIMD VRECPE 2020-06-20 15:07:06 +01:00
MerryMage d3dc50d718 A32: Implement ASIMD VRSQRTS 2020-06-20 15:06:06 +01:00
MerryMage f58e247ef3 A32: Implement ASIMD VPADD (floating-point) 2020-06-20 14:25:04 +01:00
Lioncash ed6ca58058 A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.

In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-20 00:50:40 +01:00
MerryMage 7402d38675 test_arm_instructions: Add vclt.f32 (zero) test 2020-06-18 17:59:44 +01:00
MerryMage 9f3277540a Merge A32 and A64 exclusive monitors 2020-06-17 10:33:09 +01:00
Lioncash 9b06a938a9 fuzz_arm: Ignore endian bit
A recent change from Qemu (268b1b3dfbb92a9348406f728a33f39e3d8dcd8)
allows user space modification of the E bit.
2020-06-16 01:53:21 +01:00
MerryMage 2796a85096 interface/a32: Remove descriptor argument from Disassemble 2020-06-12 15:27:42 +01:00
MerryMage e953f67201 emit_x64_packed: PackedAbsDiffSumS8: Fix case when bits above the lower 32 bits are not zero 2020-06-12 15:24:09 +01:00
MerryMage d0d50c4824 print_info: Use VFP and ASIMD decoders to get dynarmic name for instruction 2020-05-17 22:48:14 +01:00
MerryMage d0075f4ea6 print_info: Use LLVM to disassemble A32 2020-05-17 22:30:46 +01:00
MerryMage 1a0bc5ba91 A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple) 2020-05-16 14:11:23 +01:00
MerryMage e7f1a0d408 A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H} 2020-05-15 21:07:36 +01:00
Lioncash 8808b8c479 cpu_info: Make test non-allocating
Same behavior, but makes it non-allocating by using a constexpr
std::array instead of a std::vector.
2020-05-12 09:52:55 +01:00
MerryMage 7f77a04900 fuzz_arm: Do not test vfp_VMRS
This may emit a vmrs *, fpscr instruction.
This results in fuzz failures due to slight inaccuracies in fpscr emulation.
2020-05-10 14:47:21 +01:00
MerryMage 6df660c889 fuzz_arm: Ensure all instructions are fuzzed
* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
2020-05-10 13:57:39 +01:00
Fernando Sahmkow 97b9d3e058 Exclusive Monitor: Rework exclusive monitor interface. 2020-05-03 01:40:37 +01:00
MerryMage d86a6f2211 print_info: Print IR for A32 instructions 2020-04-29 15:33:56 +01:00
MerryMage 8498ac34d5 fuzz_with_unicorn: Print IR 2020-04-29 15:33:38 +01:00
MerryMage 24229ab899 constant_propagation_pass: Don't fold add if we nee flags
Results in incorrect flags
2020-04-29 15:33:12 +01:00
MerryMage 94d0d33e02 Fix single stepping for certain instructions
Several issues:
1. Several terminal instructions did not stop at the end of a single-step block
2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag

We also introduce the enable_optimizations parameter to the A32 frontend.
2020-04-24 11:44:38 +01:00
MerryMage 0d041696f5 tests/a64: Reminder about hidden infinite loops 2020-04-23 18:11:45 +01:00
MerryMage a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage 976edaf2d2 print_info: Add optimized IR output for A64 2020-04-22 21:06:18 +01:00
MerryMage 7c917f1c12 CMakeLists: Add DYNARMIC_FRONTENDS option
Allows library user to select which frontends to enable
2020-04-22 21:06:18 +01:00
MerryMage 668a43f815 A32: Detect unpredictable LDM/STM instructions 2020-04-22 21:06:18 +01:00
MerryMage 5ea3fe58c6 fuzz_with_unicorn: Add large random block testing 2020-04-22 21:06:18 +01:00
MerryMage 81fcb4e537 mp: Migrate to shared version of mp library 2020-04-22 21:06:17 +01:00
MerryMage 5d93e6e580 print_info: Add -exec parameter to test execution 2020-04-22 21:04:24 +01:00
MerryMage a59c335b05 A64: Add options for detecting misaligned loads and stores 2020-04-22 21:04:23 +01:00
MerryMage cb971d3280 test_arm_instruction: Revive some old tests 2020-04-22 21:04:23 +01:00
MerryMage 39bd2c034d constant_propagation_pass: Handle GetCarryFromOp for MostSignificantWord 2020-04-22 21:04:23 +01:00
MerryMage 1aa7b62e92 A32/Thumb: Correct behaviour for UDF and Unpredictable instructions
Raise an exception instead of calling the interpreter and ASSERT-ing respectively.
2020-04-22 21:04:23 +01:00
MerryMage c7d20f3f2f fuzz_arm: Test MSR and MRS instructions against unicorn
* Add always_little_endian option to mach unicorn behavior.
* Correct CPSR.Mode = Usermode
2020-04-22 21:04:23 +01:00