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66 commits

Author SHA1 Message Date
bunnei dfb318f208 arm: Implement STRD reg/imm instructions. 2016-08-05 20:04:59 -04:00
bunnei e931dc2496 arm: Implement STRH reg/imm instructions. 2016-08-05 20:04:58 -04:00
bunnei 9f77662b24 arm: Implement STRB reg/imm instructions. 2016-08-05 20:04:57 -04:00
bunnei caab1bbc7c arm: Implement STR reg/imm instructions. 2016-08-05 20:04:56 -04:00
bunnei b09ecb4532 arm: Implement LDR reg/imm instructions. 2016-08-05 20:04:55 -04:00
Tillmann Karras eb2e6e8bea Implement some multiplies 2016-08-05 02:09:54 +01:00
bunnei 691e4139fa arm: Implement B/BL/BX instructions. 2016-08-03 16:49:01 -04:00
Tillmann Karras fc33f1d374 Implement more instructions 
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
 2016-08-03 00:47:17 +01:00
Tillmann Karras 30a90295b9 Implement data processing instructions 
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST

The code could use some serious deduplication...
 2016-08-03 00:47:16 +01:00
MerryMage 90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage 98bd7ff6a5 Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support. 2016-07-20 12:08:17 +01:00
Merry 95316b8443 Merged in Subv/dynarmic/arm_mem_tests (pull request #4) 
Added some fuzz tests for most cases of ARM Load/Store instructions
 2016-07-20 10:19:55 +01:00
MerryMage 3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
MerryMage e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
Subv ccc61472b9 Added format strings for ARM STRBT encodings A1 and A2 2016-07-18 14:20:58 -05:00
Subv 8617bf80a1 Added format strings for ARM LDRBT encodings A1 and A2 2016-07-18 14:18:39 -05:00
Subv 5d5ea9325c Added format strings for ARM STRT encodings A1 and A2 2016-07-18 14:05:53 -05:00
MerryMage 2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. 2016-07-18 20:05:35 +01:00
Subv 77761ba032 Added the format strings for LDRT encodings A1 and A2. 2016-07-18 14:01:18 -05:00
MerryMage 14dcb18bbe Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2) 2016-07-18 18:48:08 +01:00
MerryMage a605a43ef9 Implement Thumb Instructions: STRH (imm), LDRH (imm) 2016-07-18 18:28:52 +01:00
MerryMage f9755870bb Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg) 2016-07-18 18:02:02 +01:00
MerryMage dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
MerryMage f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage 9109b226af Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm) 2016-07-18 11:16:12 +01:00
MerryMage c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage bf99ddd065 Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic 2016-07-18 10:33:52 +01:00
MerryMage 28a201da16 Implement Thumb ADR instruction 2016-07-18 09:25:33 +01:00
Subv 0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. 2016-07-17 14:45:42 -05:00
Merry 24aa24b1bc Merged in Subv/dynarmic (pull request #1) 
Implemented ARM CMP (imm) instruction.
 2016-07-17 19:43:49 +01:00
Subv 7f09510945 Implemented ARM CMP (imm) instruction. 2016-07-17 13:29:37 -05:00
MerryMage 3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage 4b1c27e64f Implement arm_ADC_imm 2016-07-14 20:02:41 +01:00
MerryMage 63242924fc Implement thumb16_SVC 2016-07-14 15:01:30 +01:00
MerryMage 9b2aff166a Implement arm_SVC 2016-07-14 14:29:46 +01:00
MerryMage 672ffb93d0 frontend/translator: Skeleton for Arm translator 2016-07-14 13:28:20 +01:00
MerryMage 8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage 44352680c6 s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones 2016-07-12 11:09:34 +01:00
MerryMage 1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage f0f14fa5e8 Implement thumb1_MOV_reg 2016-07-10 13:10:06 +08:00
MerryMage 8920ce79b9 Implement thumb_CMP_reg_t2 2016-07-10 12:23:16 +08:00
MerryMage ac2fb6b925 Implement thumb1_MVN_reg 2016-07-10 10:49:01 +08:00
MerryMage d11df9067d Implement thumb1_BIC_reg 2016-07-10 10:44:45 +08:00
MerryMage 98a64a92b1 Implement thumb1_ORR_reg 2016-07-10 09:06:38 +08:00
MerryMage 3fe46d2c6f Implement thumb1_CMN_reg 2016-07-10 08:55:56 +08:00
MerryMage 641dbf8eb4 Implement thumb1_CMP_reg 2016-07-10 08:52:28 +08:00
MerryMage 46408267c3 Implement thumb1_RSB_imm 2016-07-10 08:44:07 +08:00
MerryMage 6536ad9618 Implement thumb1_TST_reg 2016-07-10 08:35:58 +08:00
MerryMage 8145b33882 Implemented thumb1_ROR_reg 2016-07-10 08:18:17 +08:00