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1683 commits 1 branch 0 tags 34 MiB
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23 commits

Author SHA1 Message Date
Lioncash 3a2dd09122 frontend/A64/ir_emitter: Mark PC() and AlignPC() as const qualified member functions 
These don't actually alter any instance state.
 2020-04-22 20:57:38 +01:00
Lioncash f3f60cd179 A64: Implement ISB 
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
 2020-04-22 20:53:45 +01:00
MerryMage d1d6f4feb5 system: Implement MRS CNTFRQ_EL0 2020-04-22 20:53:45 +01:00
MerryMage ecbf9dbae5 IR: Implement A64OrQC 2020-04-22 20:46:22 +01:00
MerryMage e4697b1676 A64: Implement system register TPIDR_EL0 2020-04-22 20:46:15 +01:00
MerryMage e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage 9e4e4e9c1d A64: Implement system register CNTPCT_EL0 2020-04-22 20:46:15 +01:00
MerryMage 1e15283d00 A64: Implement system register CTR_EL0 2020-04-22 20:46:15 +01:00
MerryMage b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2020-04-22 20:46:14 +01:00
MerryMage 8756487554 A64: Partially implement MRS 2020-04-22 20:46:14 +01:00
MerryMage bfd65bedfe A64: Implement DSB, DMB 2020-04-22 20:46:14 +01:00
MerryMage 5edd623b9d Implement DC instructions 2020-04-22 20:46:14 +01:00
MerryMage b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
MerryMage 0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage 25411da838 A32: Implement load stores (immediate) 2020-04-22 20:42:45 +01:00
MerryMage 68391b0a05 A64: Implement SVC 2020-04-22 20:42:45 +01:00
MerryMage cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00
MerryMage 23f3afe0b3 A64: Implement branch (register) 2020-04-22 20:42:45 +01:00
MerryMage c09e69bb97 A64: Implement addsub instructions 2020-04-22 20:42:44 +01:00
MerryMage d1eb757f93 A64: Backend framework 2020-04-22 20:42:44 +01:00