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253 commits

Author SHA1 Message Date
MerryMage c78f153ddb decoder/arm: Sort decoders according to number of bits in mask 2016-12-22 15:25:38 +00:00
MerryMage cb38c94b58 decoder/arm: Fix decoding of RFE 2016-12-22 15:25:07 +00:00
MerryMage 7e77ee7fd6 decoder/arm: Fix decoding of MCR2 2016-12-22 15:11:47 +00:00
Fernando Sahmkow 677f62dd6f Implement SHSUB8 and SHSUB16 (#74) 
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
 2016-12-22 12:02:24 +00:00
MerryMage 967f3cf7e1 Implement CPS (Thumb) 
* Since currently only User mode is emulated, CPS is a NOP.
 2016-12-21 22:44:27 +00:00
MerryMage c764a2b889 Implement MUL (T1) 2016-12-21 22:44:14 +00:00
MerryMage 36082087de callbacks: Read code using MemoryReadCode callback 2016-12-21 21:39:14 +00:00
MerryMage 56ea2386d3 saturated: Implement SSAT and USAT 2016-12-21 19:51:25 +00:00
MerryMage 6a269a6ebd IR: Add microinstructions UnsignedSaturation and SignedSaturation 2016-12-21 19:51:25 +00:00
FernandoS27 8919265d2c Implement SADD8, SADD16, SSUB8, SSUB16, USUB16 2016-12-20 21:52:38 +00:00
FernandoS27 3f6ecfe245 Implemented USAD8 and USADA8 2016-12-20 21:52:38 +00:00
MerryMage 96e46ba6b5 Implement QADD, QSUB, QDADD, QDSUB 2016-12-15 22:34:29 +00:00
MerryMage b178ab3bec Replace (void)(...); idiom with UNUSED macro 2016-12-15 21:36:05 +00:00
MerryMage df197ff6b1 arm/types: Use smallest possible standard type that has sufficient bits for Imm{} types 2016-12-15 20:52:21 +00:00
MerryMage 546198d603 translate_arm: Mark arguments as unused 2016-12-15 20:52:20 +00:00
MerryMage 8d5522f4a0 dissassembler_arm: Support BKPT, QASX, QSAX, UQASX, UQSAX 2016-12-15 20:16:08 +00:00
MerryMage 52e1445f43 Implement USUB8 2016-12-05 00:29:15 +00:00
MerryMage 5c1aab1666 Implement CLZ 
Includes tests
 2016-12-04 22:56:33 +00:00
MerryMage 1a1646d962 Implement UADD8 2016-12-04 20:52:33 +00:00
MerryMage 7cad6949e7 IR: Implement new pseudo-operation GetGEFromOp 2016-12-04 20:52:06 +00:00
MerryMage e166965f3e Implement VCMP 2016-12-03 11:41:09 +00:00
MerryMage f2fe376fc6 Support 64-bit immediates 2016-12-03 11:29:50 +00:00
Mat M de1f831d79 microinstruction: Make use_count private (#53) 
Makes the operation a part of the direct interface.
 2016-11-30 21:51:06 +00:00
Merry 0ff8c375af Implement UHSUB8 and UHSUB16 (#48) 2016-11-26 18:27:21 +00:00
Merry cb17f9a3ed Implement SHADD8 and SHADD16 (#47) 2016-11-26 18:12:29 +00:00
Sebastian Valle 11ae8d1ffa Added disassembler support for the ARM parallel add/subtract (modulo arithmetic) instructions. (#50) 2016-11-26 17:58:09 +00:00
Sebastian Valle ed71e31cea Added disassembler support for the ARM parallel and saturated instructions (#44) 2016-11-26 17:49:46 +00:00
MerryMage c0c1bb1094 Implemented UHADD16 2016-11-26 11:28:20 +00:00
Yuri Kunde Schlesner 9ec51f74bd libfmt: Update version to current master 2016-11-25 20:47:04 +00:00
Sebastian Valle 4d44474ad4 Implemented the ARM UHADD8 instruction. (#45) 
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
 2016-11-25 20:32:22 +00:00
Sebastian Valle f32921d493 ARM: Implemented UXTB16. (#42) 
It passes tests.
 2016-11-24 08:21:12 +00:00
Sebastian Valle 32615d0eff Implemented the PKHTB and PKHBT instructions with tests. (#40) 2016-11-23 21:45:18 +00:00
MerryMage 780ff8e00e status_register_access: SEL: Use GetGEFlags 2016-11-23 19:47:35 +00:00
MerryMage b6f7b8babd ir: Implement GetGEFlags, SetGEFlags 2016-11-23 19:44:27 +00:00
Sebastian Valle d589c63107 Implemented the ARM SEL instruction, with tests. (#39) 
The test for this instruction is very peculiar. As the instruction's behavior depends on the value of the CPSR, we generate a MSR instruction after each SEL instruction to change the CPSR.
 2016-11-23 18:14:07 +00:00
Mat M 65dcf45ca6 FPSCR: Mask away reserved bits (#34) 2016-09-21 17:51:13 +01:00
MerryMage 792f2bfd94 translate_arm: Remove unused method ArmTranslatorVisitor::LinkToNextInstruction 2016-09-21 14:07:53 +01:00
Mat M f75acd6cfb decoder: Generify the matcher interface (#33) 
Gets rid of a bit of duplication while remaining compatible
with the current interfaces in place.
 2016-09-17 09:48:18 +01:00
Mat M 943487ecee disassembler: Provide includes to function declarations (#32) 2016-09-14 23:03:09 +01:00
Mat M 72897b5def types: Provide ostream operator<< overloads where applicable (#30) 2016-09-07 14:21:17 +01:00
Mat M 6a2174ebfa Add missing explicit specifiers (#27) 2016-09-07 12:08:48 +01:00
Mat M 6e0f27a500 types: Add helpers for determining single and doubleword extension registers (#26) 2016-09-07 12:08:35 +01:00
Mat M 5bc9ce544f arm_types: Move into arm folder (#25) 2016-09-06 00:52:33 +01:00
Mat M b40d19c3b7 location_descriptor: Provide operator<< string overload (#24) 2016-09-05 21:31:25 +01:00
Mat M 6d53bb6d7e arm_types: Split out LocationDescriptor (#20) 
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
 2016-09-05 11:54:09 +01:00
Mat M 84336cf29d value: Change Value into a class (#19) 
'struct' is a little bit of a misnomer, considering it has invariants
 2016-09-05 11:53:56 +01:00
Mat M 858796a029 Eliminate variable shadowing warnings with MSVC (#17) 2016-09-04 11:30:57 +01:00
Mat M 7f9a0c3c38 Remove unnecessary explicit includes (#16) 2016-09-03 21:48:03 +01:00
Mat M 05b189bc26 arm_types: Specialize std::hash for LocationDescriptor (#14) 
Same thing, but with the benefit of working with anything that uses
std::hash by default.
 2016-09-03 12:48:47 +01:00
Mat M 8c4df46580 FPSCR: Make value constructor explicit (#13) 
Maintains consistency between the PSR helper.
 2016-09-03 12:48:31 +01:00