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384 commits

Author SHA1 Message Date
MerryMage 52268298a8 a64_emit_x64: Perform RSB predictions 2020-04-22 20:46:12 +01:00
MerryMage 98ec9c5f90 A32: Change UserCallbacks to be similar to A64's interface 2020-04-22 20:46:12 +01:00
MerryMage 6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass 2020-04-22 20:46:12 +01:00
MerryMage e01b500aea ir_emitter: Allow the insertion point for new instructions to be set 2020-04-22 20:46:12 +01:00
Lioncash 7734cf1050 A64: Implement EXTR 2020-04-22 20:46:12 +01:00
MerryMage 88ae7fce52 A64: Implement LDP (SIMD&FP) and STP (SIMD&FP) 2020-04-22 20:44:38 +01:00
MerryMage b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
Lioncash 7abd673a49 A64: Zero upper 64 bits in ORN if using the 64-bit variant 
Resolves a TODO
 2020-04-22 20:44:38 +01:00
MerryMage ba3d6da0c8 load_store_register_unprivileged: bug: LDTRSW 2020-04-22 20:44:38 +01:00
MerryMage 75756137c6 A64: Implement CMEQ (register, vector) 2020-04-22 20:44:38 +01:00
MerryMage d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2020-04-22 20:44:38 +01:00
Fernando Sahmkow e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2020-04-22 20:44:38 +01:00
MerryMage 94383fd934 microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2020-04-22 20:44:38 +01:00
James Rowe 589ad7232f Fixup: Xn|SP are 64 bit addresses encoded in the Rn field 2020-04-22 20:44:38 +01:00
James Rowe ae880d8391 A64: Fix bugs and address review comments 2020-04-22 20:44:38 +01:00
James Rowe 3aeb7ca50c Add missing returns 2020-04-22 20:44:38 +01:00
James Rowe 41e6e659c5 A64: Implement Load/Store register (unprivileged) 2020-04-22 20:44:37 +01:00
MerryMage 285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
FernandoS27 ab84524806 Implemented SDIV and UDIV instructions 2020-04-22 20:44:37 +01:00
MerryMage 6033b05ca6 A64: Implement LDR/STR (immediate, SIMD&FP) 2020-04-22 20:44:37 +01:00
MerryMage e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage 28ccd85e5c IR: Add IR instruction ZeroExtendToQuad 2020-04-22 20:44:37 +01:00
MerryMage 3caf192f60 A64: Implement DUP (general) 2020-04-22 20:44:37 +01:00
MerryMage 793753bf63 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2020-04-22 20:44:37 +01:00
Lioncash 8ee854232c General: Default constructors and destructors where applicable 2020-04-22 20:44:37 +01:00
Lioncash d1e4526e1c ir_emitter: Remove unused includes 2020-04-22 20:44:37 +01:00
Lioncash 6f9216d544 A64: Implement RBIT 2020-04-22 20:44:37 +01:00
MerryMage 9b0a21915f ir_emitted: Remove unimplemented IR instruction Unimplemented 2020-04-22 20:44:37 +01:00
MerryMage d4b05b28cf A64: Implement CLS 
This is not the cleanest implementation.
 2020-04-22 20:42:46 +01:00
MerryMage b8e26bfdc3 A64: Implement ADDP (vector) 2020-04-22 20:42:46 +01:00
MerryMage eaf545877a IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2020-04-22 20:42:46 +01:00
MerryMage 394bd57bb6 microinstruction: bug: Add missing opcodes 2020-04-22 20:42:46 +01:00
Lioncash bb1c5bd3b2 A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL 2020-04-22 20:42:46 +01:00
Lioncash c1a25bfc2f A64: Implement MADD and MSUB 2020-04-22 20:42:46 +01:00
Lioncash b7c5055d42 A64: Implement CLZ 2020-04-22 20:42:46 +01:00
Lioncash b612782445 opcodes: Add 64-bit CountLeadingZeroes opcode 2020-04-22 20:42:46 +01:00
MerryMage 4c4efb2213 data_processing_register: Clean-up 2020-04-22 20:42:46 +01:00
Lioncash ae5dbcbed6 A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL 
Truly the most difficult A64 instructions to implement.
 2020-04-22 20:42:46 +01:00
Lioncash 4d8f4aa8af A64: Implement ASRV, LSLV, LSRV, and RORV 2020-04-22 20:42:46 +01:00
Lioncash a8a65beb2b data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG 2020-04-22 20:42:46 +01:00
MerryMage f81d0a2536 A64: Implement AND (vector) 2020-04-22 20:42:46 +01:00
MerryMage a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
Thomas Guillemard 896cf44f96 A64: Implement REV, REV32, and REV16 (#126) 2020-04-22 20:42:46 +01:00
MerryMage 5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2020-04-22 20:42:46 +01:00
MerryMage fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage 144b629d8a A64: Implement CSEL 2020-04-22 20:42:45 +01:00
MerryMage 6395f09f94 IR: Implement Conditional Select 2020-04-22 20:42:45 +01:00
MerryMage 19da68568e A64/translate/branch: bug: Read-after-write error in BLR 2020-04-22 20:42:45 +01:00