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783 commits 1 branch 0 tags 34 MiB
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652 commits

Author SHA1 Message Date
MerryMage b2d99eddc6 EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128 2020-04-22 20:46:12 +01:00
MerryMage f4f774f9f6 a64_get_set_elimination_pass: Simplify algorithm 2020-04-22 20:46:12 +01:00
MerryMage 54de64f5bf a64_emit_x64: bug: x64 sign-extends 32-bit immediates 2020-04-22 20:46:12 +01:00
MerryMage 6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass 2020-04-22 20:46:12 +01:00
MerryMage e01b500aea ir_emitter: Allow the insertion point for new instructions to be set 2020-04-22 20:46:12 +01:00
MerryMage af793c2527 {a32,a64}_interface: Predict entrypoint 2020-04-22 20:46:12 +01:00
Lioncash 7734cf1050 A64: Implement EXTR 2020-04-22 20:46:12 +01:00
MerryMage 88ae7fce52 A64: Implement LDP (SIMD&FP) and STP (SIMD&FP) 2020-04-22 20:44:38 +01:00
MerryMage d497464c9f a64_jitstate: Have 128-bit wide spills 2020-04-22 20:44:38 +01:00
MerryMage b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
MerryMage 16fa2cd8f6 a64_emit_x64: Use xword from Xbyak::util 2020-04-22 20:44:38 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
Lioncash 7abd673a49 A64: Zero upper 64 bits in ORN if using the 64-bit variant 
Resolves a TODO
 2020-04-22 20:44:38 +01:00
MerryMage ba3d6da0c8 load_store_register_unprivileged: bug: LDTRSW 2020-04-22 20:44:38 +01:00
MerryMage 75756137c6 A64: Implement CMEQ (register, vector) 2020-04-22 20:44:38 +01:00
MerryMage d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2020-04-22 20:44:38 +01:00
MerryMage 4ce9c65cfb reg_alloc: Use std::exchange 2020-04-22 20:44:38 +01:00
Fernando Sahmkow e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2020-04-22 20:44:38 +01:00
MerryMage 94383fd934 microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2020-04-22 20:44:38 +01:00
MerryMage d124a1d761 emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable 
For CPUs that didn't support SSE4.1, this was a bug.
 2020-04-22 20:44:38 +01:00
James Rowe 589ad7232f Fixup: Xn|SP are 64 bit addresses encoded in the Rn field 2020-04-22 20:44:38 +01:00
James Rowe ae880d8391 A64: Fix bugs and address review comments 2020-04-22 20:44:38 +01:00
James Rowe 3aeb7ca50c Add missing returns 2020-04-22 20:44:38 +01:00
James Rowe 41e6e659c5 A64: Implement Load/Store register (unprivileged) 2020-04-22 20:44:37 +01:00
MerryMage 01a26fa644 fixup: travis: Test with disabled CPU feature detection 2020-04-22 20:44:37 +01:00
Lioncash 5281d3c6d5 CMakeLists: Add opcodes.inc to the source file list 
Allows the file to show up nicely within IDEs
 2020-04-22 20:44:37 +01:00
MerryMage 30936f5e94 travis: Test with disabled CPU feature detection 
Ensure that fallbacks are working correctly.
 2020-04-22 20:44:37 +01:00
MerryMage 285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
MerryMage da3e9a5704 a64_emit_x64: bug: EmitA64WriteMemory128 should write not read 2020-04-22 20:44:37 +01:00
FernandoS27 ab84524806 Implemented SDIV and UDIV instructions 2020-04-22 20:44:37 +01:00
MerryMage 6033b05ca6 A64: Implement LDR/STR (immediate, SIMD&FP) 2020-04-22 20:44:37 +01:00
MerryMage f698848e26 IR: Add IR instructions A64Memory{Read,Write}128 
Add the Windows ABI implementation
 2020-04-22 20:44:37 +01:00
MerryMage e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage 28ccd85e5c IR: Add IR instruction ZeroExtendToQuad 2020-04-22 20:44:37 +01:00
MerryMage af848c627d block_of_code: Add ABI_RETURN2 2020-04-22 20:44:37 +01:00
MerryMage 1749780929 interface: Move Vector typedef to config.h 2020-04-22 20:44:37 +01:00
MerryMage 33bba6028c bit_util: bug: Infinite loop in HighestSetBit 2020-04-22 20:44:37 +01:00
MerryMage 3caf192f60 A64: Implement DUP (general) 2020-04-22 20:44:37 +01:00
MerryMage 793753bf63 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2020-04-22 20:44:37 +01:00
Lioncash 8ee854232c General: Default constructors and destructors where applicable 2020-04-22 20:44:37 +01:00
Lioncash d1e4526e1c ir_emitter: Remove unused includes 2020-04-22 20:44:37 +01:00
Lioncash 6f9216d544 A64: Implement RBIT 2020-04-22 20:44:37 +01:00
MerryMage 9b0a21915f ir_emitted: Remove unimplemented IR instruction Unimplemented 2020-04-22 20:44:37 +01:00
MerryMage db30e02ac8 emit_x64: Extract BlockRangeInformation, remove template parameter 2020-04-22 20:44:36 +01:00
MerryMage 58c4a25527 emit_x64: Use JitStateInfo 2020-04-22 20:42:46 +01:00
MerryMage d4b05b28cf A64: Implement CLS 
This is not the cleanest implementation.
 2020-04-22 20:42:46 +01:00
MerryMage b8e26bfdc3 A64: Implement ADDP (vector) 2020-04-22 20:42:46 +01:00
MerryMage eaf545877a IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2020-04-22 20:42:46 +01:00
MerryMage a554e4a329 backend_x64: Split emit_x64 2020-04-22 20:42:46 +01:00