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727 commits 1 branch 0 tags 34 MiB
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603 commits

Author SHA1 Message Date
MerryMage a554e4a329 backend_x64: Split emit_x64 2020-04-22 20:42:46 +01:00
MerryMage 394bd57bb6 microinstruction: bug: Add missing opcodes 2020-04-22 20:42:46 +01:00
Lioncash bb1c5bd3b2 A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL 2020-04-22 20:42:46 +01:00
Lioncash c1a25bfc2f A64: Implement MADD and MSUB 2020-04-22 20:42:46 +01:00
Lioncash b7c5055d42 A64: Implement CLZ 2020-04-22 20:42:46 +01:00
Lioncash b612782445 opcodes: Add 64-bit CountLeadingZeroes opcode 2020-04-22 20:42:46 +01:00
MerryMage 4c4efb2213 data_processing_register: Clean-up 2020-04-22 20:42:46 +01:00
Lioncash ae5dbcbed6 A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL 
Truly the most difficult A64 instructions to implement.
 2020-04-22 20:42:46 +01:00
Lioncash 4d8f4aa8af A64: Implement ASRV, LSLV, LSRV, and RORV 2020-04-22 20:42:46 +01:00
Lioncash a8a65beb2b data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG 2020-04-22 20:42:46 +01:00
Lioncash b08be71775 a32/a64_emit_x64: Remove unused includes 2020-04-22 20:42:46 +01:00
MerryMage f81d0a2536 A64: Implement AND (vector) 2020-04-22 20:42:46 +01:00
MerryMage a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
Thomas Guillemard 896cf44f96 A64: Implement REV, REV32, and REV16 (#126) 2020-04-22 20:42:46 +01:00
MerryMage 5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2020-04-22 20:42:46 +01:00
MerryMage 9a812b0c61 reg_alloc: GetBitWidth: Add UNREACHABLE 2020-04-22 20:42:46 +01:00
MerryMage fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage 144b629d8a A64: Implement CSEL 2020-04-22 20:42:45 +01:00
MerryMage 6395f09f94 IR: Implement Conditional Select 2020-04-22 20:42:45 +01:00
MerryMage 19da68568e A64/translate/branch: bug: Read-after-write error in BLR 2020-04-22 20:42:45 +01:00
MerryMage 9f57283a30 A64: Implement SBFM, BFM, UBFM 2020-04-22 20:42:45 +01:00
MerryMage cdbc8d07a5 A64: Implement MOVN, MOVZ, MOVK 2020-04-22 20:42:45 +01:00
MerryMage ecebe14a01 ir/location_descriptor: Add missing <functional> header for std::hash 2020-04-22 20:42:45 +01:00
MerryMage 4e3675da7b a64_merge_interpret_blocks: Remove debug output 2020-04-22 20:42:45 +01:00
MerryMage c6a091d874 A64: Optimization: Merge interpret blocks 2020-04-22 20:42:45 +01:00
MerryMage 21fe61eac6 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate 2020-04-22 20:42:45 +01:00
MerryMage 7c4b70751c A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 2020-04-22 20:42:45 +01:00
MerryMage 996ffd5488 a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 2020-04-22 20:42:45 +01:00
MerryMage e4615a4562 emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 2020-04-22 20:42:45 +01:00
MerryMage 0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage 61125d6dd1 A64/translate: Add TranslateSingleInstruction function 2020-04-22 20:42:45 +01:00
MerryMage aa74a8130b Misc. fixups of MSVC build 2020-04-22 20:42:45 +01:00
MerryMage a1dfa01515 imm: Suppress MSVC warning C4244: value will never be truncated 2020-04-22 20:42:45 +01:00
MerryMage 26da149639 imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions 2020-04-22 20:42:45 +01:00
MerryMage b34c6616d4 A64/decoder: Split decoder data from header 2020-04-22 20:42:45 +01:00
MerryMage 72a793f5b0 ir_opt: Split off A32 specific passes 2020-04-22 20:42:45 +01:00
MerryMage 595f157e5e A64: Implement LDP, STP 2020-04-22 20:42:45 +01:00
MerryMage 511215342b A64/location_descriptor: Fix -fpermissive warning on GCC 2020-04-22 20:42:45 +01:00
MerryMage 243f06c613 A64: Implement LDP, STP 2020-04-22 20:42:45 +01:00
MerryMage 25411da838 A32: Implement load stores (immediate) 2020-04-22 20:42:45 +01:00
MerryMage 2aadeec291 A64: Implement SVC 2020-04-22 20:42:45 +01:00
MerryMage 9e27e4d250 imm: bug: SignExtend wasn't working for T with bit size > 32 2020-04-22 20:42:45 +01:00
MerryMage 10c60dda97 a64_emit_x64: Don't use far code for now 2020-04-22 20:42:45 +01:00
MerryMage 593a569b53 EmitA64SetW: bug: should zero extend to entire 64-bit register 2020-04-22 20:42:45 +01:00
MerryMage 6bd9f02911 EmitA64SetNZCV: bug: to_store is scratch 2020-04-22 20:42:45 +01:00
MerryMage f0276dd53b emit_x86: Fix nzcv for EmitSub 2020-04-22 20:42:45 +01:00
MerryMage 68391b0a05 A64: Implement SVC 2020-04-22 20:42:45 +01:00
MerryMage e5ace37560 a64_emit_x64: Call interpreter 2020-04-22 20:42:45 +01:00
MerryMage b12dead76a A64: Add batch register retrieval to interface 2020-04-22 20:42:45 +01:00
MerryMage cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00