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808 commits 1 branch 0 tags 34 MiB
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672 commits

Author SHA1 Message Date
MerryMage 99d8ebe4d5 A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar) 2020-04-22 20:46:13 +01:00
MerryMage 429dc24587 IR: Merge U32 and U64 variants of FP instructions 2020-04-22 20:46:13 +01:00
MerryMage ed2bedec43 A64: Implement {ST,LD}{1,2,3,4} (multiple structures) 2020-04-22 20:46:13 +01:00
MerryMage 6414736a8d emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1 
This bug wasn't discovered earlier because we previously only used index == 0.
 2020-04-22 20:46:13 +01:00
MerryMage ebfc51c609 IR: Implement VectorSetElement{8,16,32,64} 2020-04-22 20:46:13 +01:00
Lioncash a5c4fbc783 A64: Implement AESIMC and AESMC 2020-04-22 20:46:13 +01:00
Lioncash 744495e23d iterator_util: Make Reverse constexpr 
C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.
 2020-04-22 20:46:12 +01:00
Lioncash ab9b5fb8aa Common: Relocate common bits of CRC32 
Allows the algorithm to be used in any other potential backend.
 2020-04-22 20:46:12 +01:00
Lioncash af1384d700 A64: Implement CRC32 2020-04-22 20:46:12 +01:00
MerryMage 64761dbc72 scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT 2020-04-22 20:46:12 +01:00
MerryMage bafb39ebc5 A64: Add Disassemble method 2020-04-22 20:46:12 +01:00
MerryMage cc0eb18a0b A32: data_processing: Remove !S assertions 2020-04-22 20:46:12 +01:00
MerryMage 865a30eb0d A32: Implement BKPT 2020-04-22 20:46:12 +01:00
MerryMage f023bbb893 A32: Add ExceptionRaised IR instruction and use it 2020-04-22 20:46:12 +01:00
Lioncash 7ffbebf290 A64: Implement CRC32C 2020-04-22 20:46:12 +01:00
MerryMage d7044bc751 assert: Use fmt in ASSERT_MSG 2020-04-22 20:46:12 +01:00
MerryMage 52268298a8 a64_emit_x64: Perform RSB predictions 2020-04-22 20:46:12 +01:00
MerryMage 98ec9c5f90 A32: Change UserCallbacks to be similar to A64's interface 2020-04-22 20:46:12 +01:00
Lioncash b9ce660113 reg_alloc: std::move RegAlloc's function argument 2020-04-22 20:46:12 +01:00
Lioncash ed561d6653 General: Add missing override specifiers 2020-04-22 20:46:12 +01:00
MerryMage b2d99eddc6 EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128 2020-04-22 20:46:12 +01:00
MerryMage f4f774f9f6 a64_get_set_elimination_pass: Simplify algorithm 2020-04-22 20:46:12 +01:00
MerryMage 54de64f5bf a64_emit_x64: bug: x64 sign-extends 32-bit immediates 2020-04-22 20:46:12 +01:00
MerryMage 6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass 2020-04-22 20:46:12 +01:00
MerryMage e01b500aea ir_emitter: Allow the insertion point for new instructions to be set 2020-04-22 20:46:12 +01:00
MerryMage af793c2527 {a32,a64}_interface: Predict entrypoint 2020-04-22 20:46:12 +01:00
Lioncash 7734cf1050 A64: Implement EXTR 2020-04-22 20:46:12 +01:00
MerryMage 88ae7fce52 A64: Implement LDP (SIMD&FP) and STP (SIMD&FP) 2020-04-22 20:44:38 +01:00
MerryMage d497464c9f a64_jitstate: Have 128-bit wide spills 2020-04-22 20:44:38 +01:00
MerryMage b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
MerryMage 16fa2cd8f6 a64_emit_x64: Use xword from Xbyak::util 2020-04-22 20:44:38 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
Lioncash 7abd673a49 A64: Zero upper 64 bits in ORN if using the 64-bit variant 
Resolves a TODO
 2020-04-22 20:44:38 +01:00
MerryMage ba3d6da0c8 load_store_register_unprivileged: bug: LDTRSW 2020-04-22 20:44:38 +01:00
MerryMage 75756137c6 A64: Implement CMEQ (register, vector) 2020-04-22 20:44:38 +01:00
MerryMage d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2020-04-22 20:44:38 +01:00
MerryMage 4ce9c65cfb reg_alloc: Use std::exchange 2020-04-22 20:44:38 +01:00
Fernando Sahmkow e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2020-04-22 20:44:38 +01:00
MerryMage 94383fd934 microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2020-04-22 20:44:38 +01:00
MerryMage d124a1d761 emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable 
For CPUs that didn't support SSE4.1, this was a bug.
 2020-04-22 20:44:38 +01:00
James Rowe 589ad7232f Fixup: Xn|SP are 64 bit addresses encoded in the Rn field 2020-04-22 20:44:38 +01:00
James Rowe ae880d8391 A64: Fix bugs and address review comments 2020-04-22 20:44:38 +01:00
James Rowe 3aeb7ca50c Add missing returns 2020-04-22 20:44:38 +01:00
James Rowe 41e6e659c5 A64: Implement Load/Store register (unprivileged) 2020-04-22 20:44:37 +01:00
MerryMage 01a26fa644 fixup: travis: Test with disabled CPU feature detection 2020-04-22 20:44:37 +01:00
Lioncash 5281d3c6d5 CMakeLists: Add opcodes.inc to the source file list 
Allows the file to show up nicely within IDEs
 2020-04-22 20:44:37 +01:00
MerryMage 30936f5e94 travis: Test with disabled CPU feature detection 
Ensure that fallbacks are working correctly.
 2020-04-22 20:44:37 +01:00
MerryMage 285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
MerryMage da3e9a5704 a64_emit_x64: bug: EmitA64WriteMemory128 should write not read 2020-04-22 20:44:37 +01:00
FernandoS27 ab84524806 Implemented SDIV and UDIV instructions 2020-04-22 20:44:37 +01:00