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Author SHA1 Message Date
Lioncash 2ac615b882 thumb32: Implement SSAT/USAT 2021-03-01 15:59:52 -05:00
Lioncash 5601aa554e thumb32: Implement STRB/STRH/STR (register) 2021-03-01 15:41:49 -05:00
MerryMage 2fbb79fdf2 externals: Build vixl 2021-03-01 20:36:21 +00:00
MerryMage 1ca401619d Merge commit 'e64a00a7fcc1cfa7ac5f81626f85075997f9d8a3' as 'externals/vixl/vixl' 2021-03-01 20:20:36 +00:00
MerryMage 170ab30b8e thumb32: Implement RSB (immediate) 2021-02-28 21:49:14 +00:00
MerryMage 8d33de2dcc thumb32: Implement SUB (immediate, T3) 2021-02-28 21:49:14 +00:00
MerryMage 8efb2a5b05 thumb32: Implement CMP (immediate) 2021-02-28 21:49:14 +00:00
MerryMage 78330e634f thumb32: Implement SBC (immediate) 2021-02-28 21:49:14 +00:00
MerryMage e6b925146b thumb32: Implement ADC (immediate) 2021-02-28 21:49:14 +00:00
MerryMage 8f9e052c93 thumb32: Implement ADD (imm, T3) 2021-02-28 21:49:14 +00:00
MerryMage 30442ee1f4 thumb32: Implement CMN (immediate) 2021-02-28 21:49:14 +00:00
merry 421548ceef
Merge pull request #581 from lioncash/8dot6 
a64: Add v8.6 instruction encoding additions
 2021-02-27 21:54:08 +00:00
Lioncash 385f907463 a64: Add v8.6 instruction encoding additions 
Keeps the instruction listing up to date.
 2021-02-27 16:25:13 -05:00
merry bf7d1a17ba
Merge pull request #580 from lioncash/shift 
thumb32: Implement ASR, LSL, LSR, and ROR register variants
 2021-02-26 19:07:12 +00:00
Lioncash 9d5505422f thumb32: Implement ADD/SUB (imm 2) 2021-02-25 09:56:05 -05:00
Lioncash 68885fdb3c thumb32: Implement SBFX/UBFX 2021-02-25 09:37:15 -05:00
Lioncash 7334914047 thumb32: Implement BFC/BFI 2021-02-25 09:27:05 -05:00
Lioncash ba7cbe7cf6 thumb32: Implement SSAT16/USAT16 2021-02-25 09:13:46 -05:00
Lioncash 725d712c88 thumb32: Simplify register shift implementations to common function 2021-02-23 04:53:50 -05:00
Lioncash a7a9ed69b7 thumb32: Implement ROR (register) 2021-02-23 04:52:29 -05:00
Lioncash abf3548b2a thumb32: Implement ASR (register) 2021-02-23 04:43:11 -05:00
Lioncash e06d4bcbb2 thumb32: Implement LSR (register) 2021-02-23 04:40:43 -05:00
Lioncash fdd379a36c thumb32: Implement LSL (register) 2021-02-23 04:40:40 -05:00
merry ac32175eff
Merge pull request #579 from lioncash/bxj 
thumb32: Implement BXJ
 2021-02-22 15:01:08 +00:00
merry e753b223e2
Merge pull request #578 from lioncash/hint 
thumb32: Implement hint instructions
 2021-02-22 14:31:49 +00:00
Lioncash 89838c5ce4 thumb32: Implement BXJ 
We handle this as a regular BX call, given we don't support Jazelle.
 2021-02-22 07:45:21 -05:00
Lioncash de8e977bb1 thumb32: Implement SEVL 2021-02-22 07:34:42 -05:00
Lioncash a4c9ec645f thumb32: Implement SEV 2021-02-22 07:34:42 -05:00
Lioncash 565a20b096 thumb32: Implement WFI 2021-02-22 07:34:42 -05:00
Lioncash 3dc33c1257 thumb32: Implement WFE 2021-02-22 07:34:42 -05:00
Lioncash 48fe7afe72 thumb32: Implement YIELD 2021-02-22 07:34:42 -05:00
Lioncash a73ea9e111 thumb32: Implement NOP 2021-02-22 07:34:39 -05:00
MerryMage 29d7cbd899 thumb32: Ensure CPSR.IT state is always up to date 2021-02-22 00:27:16 +00:00
MerryMage f5dd7122a2 EmitFPVectorMulAdd: Correct optimization flag (Unsafe_UnfuseFMA -> Unsafe_InaccurateNaN) 2021-02-21 21:30:20 +00:00
merry 75f4978da5
Merge pull request #577 from lioncash/barrier 
thumb32: Implement barrier instructions and CLREX
 2021-02-19 22:51:13 +00:00
merry 4b43dd33c6
Merge pull request #576 from lioncash/pbi 
thumb32: Implement MOVT/MOVW
 2021-02-19 22:48:43 +00:00
Lioncash 3890590b4f thumb32: Implement CLREX 2021-02-19 00:02:57 -05:00
Lioncash 5543e4f9eb thumb32: Implement ISB 2021-02-19 00:01:24 -05:00
Lioncash 085147b5a4 thumb32: Implement DMB 2021-02-18 23:59:34 -05:00
Lioncash 368a8630e0 thumb32: Implement DSB 2021-02-18 23:58:12 -05:00
Lioncash 5602db88f4 thumb32: Implement MOVW 2021-02-18 23:52:06 -05:00
Lioncash d05c706ff4 thumb32: Implement MOVT 2021-02-18 23:52:03 -05:00
MerryMage f568687bd9 thumb32: Implement EOR (immediate) 2021-02-18 20:51:13 +00:00
MerryMage 8fd7ec3989 thumb32: Implement TEQ (immediate) 2021-02-18 20:49:06 +00:00
MerryMage efbc8cef53 thumb32: Implement ORN (immediate) 2021-02-18 20:48:55 +00:00
MerryMage 08f046036c thumb32: Implement MVN (immediate) 2021-02-18 20:19:45 +00:00
MerryMage cafa687684 thumb32: Implement ORR (immediate) 2021-02-18 01:28:03 +00:00
MerryMage b2f0575fee thumb32: Implement MOV (immediate) 2021-02-18 01:28:03 +00:00
MerryMage 3dcc882fbf thumb32: Implement BIC (immediate) 2021-02-18 01:28:03 +00:00
MerryMage 6f3c5dc1d9 thumb32: Implement AND (immediate) 2021-02-18 01:28:03 +00:00